[PULL 31/56] MAINTAINERS: Add common-user/host/riscv to RISC-V section

From: Alistair Francis <alistair23@gmail.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250422024752.2060289-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 57dddcc80d..7060cf49b9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -328,6 +328,7 @@ F: include/hw/char/riscv_htif.h
 F: include/hw/riscv/
 F: linux-user/host/riscv32/
 F: linux-user/host/riscv64/
+F: common-user/host/riscv*
 F: tests/functional/test_riscv*
 F: tests/tcg/riscv64/
 
-- 
2.49.0

• [PULL 01/56] hw/riscv/virt: Add the BDF of IOMMU to RISCVVirtState structure
• [PULL 02/56] hw/riscv/virt-acpi-build: Add support for RIMT
• [PULL 03/56] target/riscv: pmp: don't allow RLB to bypass rule privileges
• [PULL 04/56] target/riscv: pmp: move Smepmp operation conversion into a function
• [PULL 05/56] target/riscv: pmp: fix checks on writes to pmpcfg in Smepmp MML mode
• [PULL 06/56] target/riscv: pmp: exit csr writes early if value was not changed
• [PULL 07/56] target/riscv: pmp: remove redundant check in pmp_is_locked
• [PULL 08/56] Generate strided vector loads/stores with tcg nodes.
• [PULL 09/56] hw/misc: Add MPFS system reset support
• [PULL 10/56] hw/riscv: More flexible FDT placement for MPFS
• [PULL 11/56] hw/riscv: Make FDT optional for MPFS
• [PULL 12/56] hw/riscv: Allow direct start of kernel for MPFS
• [PULL 13/56] hw/riscv: Configurable MPFS CLINT timebase freq
• [PULL 14/56] hw/riscv: microchip_pfsoc: Rework documentation
• [PULL 15/56] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.
• [PULL 16/56] Expand the probe_pages helper function to handle probe flags.
• [PULL 17/56] hw/riscv: Fix type conflict of GLib function pointers
• [PULL 18/56] target/riscv: fix endless translation loop on big endian systems
• [PULL 19/56] common-user/host/riscv: use tail pseudoinstruction for calling tail
• [PULL 20/56] target/riscv: rvv: Source vector registers cannot overlap mask register
• [PULL 21/56] target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS
• [PULL 22/56] target/riscv: rvv: Apply vext_check_input_eew to vrgather instructions to check mismatched input EEWs encoding constraint
• [PULL 23/56] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions
• [PULL 24/56] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions
• [PULL 25/56] target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX)
• [PULL 26/56] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)
• [PULL 27/56] target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen instructions
• [PULL 28/56] target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions
• [PULL 29/56] target/riscv: Fix the rvv reserved encoding of unmasked instructions
• [PULL 30/56] target/riscv: Fix vslidedown with rvv_ta_all_1s
• [PULL 31/56] MAINTAINERS: Add common-user/host/riscv to RISC-V section
• [PULL 32/56] target/riscv: Pass ra to riscv_csr_write_fn
• [PULL 33/56] target/riscv: Pass ra to riscv_csrrw_do64
• [PULL 34/56] target/riscv: Pass ra to riscv_csrrw_do128
• [PULL 35/56] target/riscv: Pass ra to riscv_csrrw
• [PULL 36/56] target/riscv: Pass ra to riscv_csrrw_i128
• [PULL 37/56] target/riscv: Move insn_len to internals.h
• [PULL 38/56] target/riscv: Fix write_misa vs aligned next_pc
• [PULL 39/56] target/riscv/kvm: minor fixes/tweaks
• [PULL 40/56] target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
• [PULL 41/56] target/riscv/kvm: turn u32/u64 reg functions into macros
• [PULL 42/56] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro
• [PULL 43/56] target/riscv/kvm: add kvm_csr_cfgs[]
• [PULL 44/56] target/riscv/kvm: do not read unavailable CSRs
• [PULL 45/56] target/riscv/kvm: add senvcfg CSR
• [PULL 46/56] target/riscv/kvm: read/write KVM regs via env size
• [PULL 47/56] target/riscv/kvm: add scounteren CSR
• [PULL 48/56] hw/riscv/virt.c: enforce s->memmap use in machine_init()
• [PULL 49/56] hw/riscv/virt.c: remove trivial virt_memmap references
• [PULL 50/56] hw/riscv/virt.c: use s->memmap in virt_machine_done()
• [PULL 51/56] hw/riscv/virt.c: add 'base' arg in create_fw_cfg()
• [PULL 52/56] hw/riscv/virt.c: use s->memmap in create_fdt() path
• [PULL 53/56] hw/riscv/virt.c: use s->memmap in create_fdt_sockets() path
• [PULL 54/56] hw/riscv/virt.c: use s->memmap in create_fdt_virtio()
• [PULL 55/56] hw/riscv/virt.c: use s->memmap in finalize_fdt() functions
• [PULL 56/56] hw/riscv/virt.c: remove 'long' casts in fmt strings