From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 757a34115e7491744a63dfc3d291fd1de5297ee2:

  Merge tag 'pull-nvme-20250515' of https://gitlab.com/birkelund/qemu into staging (2025-05-15 13:42:27 -0400)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20250519

for you to fetch changes up to e7cb99bfd1afc5cf2265a122bcfeab36eff7489a:

  hw/riscv/virt.c: remove 'long' casts in fmt strings (2025-05-19 13:42:56 +1000)

----------------------------------------------------------------
First RISC-V PR for 10.1

* Add support for RIMT to virt machine ACPI
* Don't allow PMP RLB to bypass rule privileges
* Fix checks on writes to pmpcfg in Smepmp MML mode
* Generate strided vector loads/stores with tcg nodes
* Improve Microchip Polarfire SoC customization
* Use tcg ops generation to emulate whole reg rvv loads/stores
* Expand the probe_pages helper function to handle probe flags
* Fix type conflict of GLib function pointers
* Fix endless translation loop on big endian systems
* Use tail pseudoinstruction for calling tail
* Fix some RISC-V vector instruction corner cases
* MAINTAINERS: Add common-user/host/riscv to RISC-V section
* Fix write_misa vs aligned next_pc
* KVM CSR fixes
* Virt machine memmap usage cleanup

----------------------------------------------------------------
Alistair Francis (1):
      MAINTAINERS: Add common-user/host/riscv to RISC-V section

Anton Blanchard (3):
      target/riscv: rvv: Source vector registers cannot overlap mask register
      target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS
      target/riscv: Fix vslidedown with rvv_ta_all_1s

Daniel Henrique Barboza (18):
      target/riscv/kvm: minor fixes/tweaks
      target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
      target/riscv/kvm: turn u32/u64 reg functions into macros
      target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro
      target/riscv/kvm: add kvm_csr_cfgs[]
      target/riscv/kvm: do not read unavailable CSRs
      target/riscv/kvm: add senvcfg CSR
      target/riscv/kvm: read/write KVM regs via env size
      target/riscv/kvm: add scounteren CSR
      hw/riscv/virt.c: enforce s->memmap use in machine_init()
      hw/riscv/virt.c: remove trivial virt_memmap references
      hw/riscv/virt.c: use s->memmap in virt_machine_done()
      hw/riscv/virt.c: add 'base' arg in create_fw_cfg()
      hw/riscv/virt.c: use s->memmap in create_fdt() path
      hw/riscv/virt.c: use s->memmap in create_fdt_sockets() path
      hw/riscv/virt.c: use s->memmap in create_fdt_virtio()
      hw/riscv/virt.c: use s->memmap in finalize_fdt() functions
      hw/riscv/virt.c: remove 'long' casts in fmt strings

Icenowy Zheng (1):
      common-user/host/riscv: use tail pseudoinstruction for calling tail

Loïc Lefort (5):
      target/riscv: pmp: don't allow RLB to bypass rule privileges
      target/riscv: pmp: move Smepmp operation conversion into a function
      target/riscv: pmp: fix checks on writes to pmpcfg in Smepmp MML mode
      target/riscv: pmp: exit csr writes early if value was not changed
      target/riscv: pmp: remove redundant check in pmp_is_locked

Max Chou (8):
      target/riscv: rvv: Apply vext_check_input_eew to vrgather instructions to check mismatched input EEWs encoding constraint
      target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions
      target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions
      target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX)
      target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)
      target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen instructions
      target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions
      target/riscv: Fix the rvv reserved encoding of unmasked instructions

Paolo Bonzini (1):
      hw/riscv: Fix type conflict of GLib function pointers

Paolo Savini (3):
      Generate strided vector loads/stores with tcg nodes.
      target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.
      Expand the probe_pages helper function to handle probe flags.

Richard Henderson (7):
      target/riscv: Pass ra to riscv_csr_write_fn
      target/riscv: Pass ra to riscv_csrrw_do64
      target/riscv: Pass ra to riscv_csrrw_do128
      target/riscv: Pass ra to riscv_csrrw
      target/riscv: Pass ra to riscv_csrrw_i128
      target/riscv: Move insn_len to internals.h
      target/riscv: Fix write_misa vs aligned next_pc

Sebastian Huber (6):
      hw/misc: Add MPFS system reset support
      hw/riscv: More flexible FDT placement for MPFS
      hw/riscv: Make FDT optional for MPFS
      hw/riscv: Allow direct start of kernel for MPFS
      hw/riscv: Configurable MPFS CLINT timebase freq
      hw/riscv: microchip_pfsoc: Rework documentation

Sunil V L (2):
      hw/riscv/virt: Add the BDF of IOMMU to RISCVVirtState structure
      hw/riscv/virt-acpi-build: Add support for RIMT

Ziqiao Kong (1):
      target/riscv: fix endless translation loop on big endian systems

 MAINTAINERS                                |   1 +
 docs/system/riscv/microchip-icicle-kit.rst | 124 ++----
 include/hw/riscv/microchip_pfsoc.h         |   1 +
 include/hw/riscv/virt.h                    |   1 +
 target/riscv/cpu.h                         |  16 +-
 target/riscv/internals.h                   |   5 +
 target/riscv/insn32.decode                 |  18 +-
 hw/misc/mchp_pfsoc_sysreg.c                |   7 +
 hw/riscv/microchip_pfsoc.c                 | 153 +++++--
 hw/riscv/riscv_hart.c                      |   9 +-
 hw/riscv/virt-acpi-build.c                 | 215 ++++++++++
 hw/riscv/virt.c                            | 273 ++++++------
 target/riscv/cpu_helper.c                  |   6 +-
 target/riscv/csr.c                         | 278 +++++++------
 target/riscv/kvm/kvm-cpu.c                 | 333 +++++++++------
 target/riscv/op_helper.c                   |  13 +-
 target/riscv/pmp.c                         | 147 ++++---
 target/riscv/translate.c                   |   5 -
 target/riscv/vector_helper.c               |  63 ++-
 target/riscv/insn_trans/trans_rvbf16.c.inc |   9 +-
 target/riscv/insn_trans/trans_rvv.c.inc    | 644 +++++++++++++++++++++++------
 common-user/host/riscv/safe-syscall.inc.S  |   4 +-
 22 files changed, 1570 insertions(+), 755 deletions(-)

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any user-visible changes.

On 19.05.2025 07:04, alistair23@gmail.com wrote:
> From: Alistair Francis <alistair.francis@wdc.com>

> First RISC-V PR for 10.1
> 
> * Add support for RIMT to virt machine ACPI
> * Don't allow PMP RLB to bypass rule privileges
> * Fix checks on writes to pmpcfg in Smepmp MML mode
> * Generate strided vector loads/stores with tcg nodes
> * Improve Microchip Polarfire SoC customization
> * Use tcg ops generation to emulate whole reg rvv loads/stores
> * Expand the probe_pages helper function to handle probe flags
> * Fix type conflict of GLib function pointers
> * Fix endless translation loop on big endian systems
> * Use tail pseudoinstruction for calling tail
> * Fix some RISC-V vector instruction corner cases
> * MAINTAINERS: Add common-user/host/riscv to RISC-V section
> * Fix write_misa vs aligned next_pc
> * KVM CSR fixes
> * Virt machine memmap usage cleanup

Hi!

Alistar, there are multiple patches in this pull request which
are tagged for stable.  Many of them (if not all) does not have
a Fixes: tag, or any other indication where they're applicable.
Is there some hint I can use to decide which active stable release
to apply to, for each patch?  Maybe we should apply most of them
just to the latest releases (current: 9.2, to be end-of-line
after the next release, and 10.0), or some of them should be
applied for older release (current: 7.2)?

Thanks,

/mjt

On Tue, May 20, 2025 at 3:08 PM Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> On 19.05.2025 07:04, alistair23@gmail.com wrote:
> > From: Alistair Francis <alistair.francis@wdc.com>
>
> > First RISC-V PR for 10.1
> >
> > * Add support for RIMT to virt machine ACPI
> > * Don't allow PMP RLB to bypass rule privileges
> > * Fix checks on writes to pmpcfg in Smepmp MML mode
> > * Generate strided vector loads/stores with tcg nodes
> > * Improve Microchip Polarfire SoC customization
> > * Use tcg ops generation to emulate whole reg rvv loads/stores
> > * Expand the probe_pages helper function to handle probe flags
> > * Fix type conflict of GLib function pointers
> > * Fix endless translation loop on big endian systems
> > * Use tail pseudoinstruction for calling tail
> > * Fix some RISC-V vector instruction corner cases
> > * MAINTAINERS: Add common-user/host/riscv to RISC-V section
> > * Fix write_misa vs aligned next_pc
> > * KVM CSR fixes
> > * Virt machine memmap usage cleanup
>
> Hi!
>
> Alistar, there are multiple patches in this pull request which
> are tagged for stable.  Many of them (if not all) does not have
> a Fixes: tag, or any other indication where they're applicable.

Yeah, I tried to Cc stable if it was a fix.

> Is there some hint I can use to decide which active stable release
> to apply to, for each patch?  Maybe we should apply most of them

My initial thinking was to apply all of the patches tagged for stable
if they apply cleanly. If the patch doesn't apply cleanly then just
skip it. Don't bother trying to get it to apply.

> just to the latest releases (current: 9.2, to be end-of-line
> after the next release, and 10.0), or some of them should be
> applied for older release (current: 7.2)?

That is also fine with me. Most of the fixes are for vector
instructions, which is a fast moving target anyway, so just getting
them in the latest release will be fine.

Patches with a Fixes tag should be applied to branches with the
relevant commits though.

Alistair

>
> Thanks,
>
> /mjt