On 4/29/25 3:12 AM, Joel Stanley wrote:
> The current device tree property uses two cells for the address (and for
> the size), but assumes the they are less than 32 bits by hard coding the
> high cell to zero.
>
> Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
> and lower 32 bits across cells.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> hw/riscv/virt.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index f8943f81790c..cd19c266e62a 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -894,8 +894,8 @@ static void create_fdt_pcie(RISCVVirtState *s,
> if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
> qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle);
> }
> - qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0,
> - s->memmap[VIRT_PCIE_ECAM].base, 0, s->memmap[VIRT_PCIE_ECAM].size);
> + qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2,
> + s->memmap[VIRT_PCIE_ECAM].base, 2, s->memmap[VIRT_PCIE_ECAM].size);
> qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges",
> 1, FDT_PCI_RANGE_IOPORT, 2, 0,
> 2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].size,