[v1] vfio/igd: Detect IGD by OpRegion and enable OpRegion automatically

[PATCH 7/9] vfio/igd: Allow overriding GMS with 0xf0 to 0xfe on Gen9+

Posted by Tomita Moeko 9 months, 2 weeks ago

On Gen9 and later IGD devices, GMS 0xf0 to 0xfe represents 4MB to 60MB
pre-allocated memory size in 4MB increments. Allow users overriding
GMS with these values.

Signed-off-by: Tomita Moeko <tomitamoeko@gmail.com>
---
 hw/vfio/igd.c | 59 +++++++++++++++++++++++++++++++++++----------------
 1 file changed, 41 insertions(+), 18 deletions(-)

diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c
index 496d3df598..7f289a62a3 100644
--- a/hw/vfio/igd.c
+++ b/hw/vfio/igd.c
@@ -411,6 +411,44 @@ static bool vfio_pci_igd_setup_lpc_bridge(VFIOPCIDevice *vdev, Error **errp)
     return true;
 }
 
+static bool vfio_pci_igd_override_gms(int gen, uint32_t gms, uint32_t *gmch)
+{
+    bool ret = false;
+
+    if (gen == -1) {
+        error_report("x-igd-gms is not supported on this device");
+    } else if (gen < 8) {
+        if (gms <= 0x10) {
+            *gmch &= ~(IGD_GMCH_GEN6_GMS_MASK << IGD_GMCH_GEN6_GMS_SHIFT);
+            *gmch |= gms << IGD_GMCH_GEN6_GMS_SHIFT;
+            ret = true;
+        } else {
+            error_report(QERR_INVALID_PARAMETER_VALUE, "x-igd-gms", "0~0x10");
+        }
+    } else if (gen == 8) {
+        if (gms <= 0x40) {
+            *gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT);
+            *gmch |= gms << IGD_GMCH_GEN8_GMS_SHIFT;
+            ret = true;
+        } else {
+            error_report(QERR_INVALID_PARAMETER_VALUE, "x-igd-gms", "0~0x40");
+        }
+    } else {
+        /* 0x0  to 0x40: 32MB increments starting at 0MB */
+        /* 0xf0 to 0xfe: 4MB increments starting at 4MB */
+        if ((gms <= 0x40) || (gms >= 0xf0 && gms <= 0xfe)) {
+            *gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT);
+            *gmch |= gms << IGD_GMCH_GEN8_GMS_SHIFT;
+            ret = true;
+        } else {
+            error_report(QERR_INVALID_PARAMETER_VALUE,
+                         "x-igd-gms", "0~0x40 or 0xf0~0xfe");
+        }
+    }
+
+    return ret;
+}
+
 #define IGD_GGC_MMIO_OFFSET     0x108040
 #define IGD_BDSM_MMIO_OFFSET    0x1080C0
 
@@ -593,24 +631,9 @@ static bool vfio_pci_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp)
      * 32MiB. This option should only be used when the desired size cannot be
      * set from DVMT Pre-Allocated option in host BIOS.
      */
-    if (vdev->igd_gms) {
-        if (gen < 8) {
-            if (vdev->igd_gms <= 0x10) {
-                gmch &= ~(IGD_GMCH_GEN6_GMS_MASK << IGD_GMCH_GEN6_GMS_SHIFT);
-                gmch |= vdev->igd_gms << IGD_GMCH_GEN6_GMS_SHIFT;
-            } else {
-                error_report(QERR_INVALID_PARAMETER_VALUE,
-                             "x-igd-gms", "0~0x10");
-            }
-        } else {
-            if (vdev->igd_gms <= 0x40) {
-                gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT);
-                gmch |= vdev->igd_gms << IGD_GMCH_GEN8_GMS_SHIFT;
-            } else {
-                error_report(QERR_INVALID_PARAMETER_VALUE,
-                             "x-igd-gms", "0~0x40");
-            }
-        }
+    if (vdev->igd_gms &&
+        !vfio_pci_igd_override_gms(gen, vdev->igd_gms, &gmch)) {
+        return false;
     }
 
     gms_size = igd_stolen_memory_size(gen, gmch);
-- 
2.47.2

Re: [PATCH 7/9] vfio/igd: Allow overriding GMS with 0xf0 to 0xfe on Gen9+

Posted by Corvin Köhne 9 months, 1 week ago

On Tue, 2025-04-29 at 00:10 +0800, Tomita Moeko wrote:
> CAUTION: External Email!!
> On Gen9 and later IGD devices, GMS 0xf0 to 0xfe represents 4MB to 60MB
> pre-allocated memory size in 4MB increments. Allow users overriding
> GMS with these values.
> 
> Signed-off-by: Tomita Moeko <tomitamoeko@gmail.com>
> ---
>  hw/vfio/igd.c | 59 +++++++++++++++++++++++++++++++++++----------------
>  1 file changed, 41 insertions(+), 18 deletions(-)
> 
> diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c
> index 496d3df598..7f289a62a3 100644
> --- a/hw/vfio/igd.c
> +++ b/hw/vfio/igd.c
> @@ -411,6 +411,44 @@ static bool vfio_pci_igd_setup_lpc_bridge(VFIOPCIDevice
> *vdev, Error **errp)
>      return true;
>  }
>  
> +static bool vfio_pci_igd_override_gms(int gen, uint32_t gms, uint32_t *gmch)
> +{
> +    bool ret = false;
> +
> +    if (gen == -1) {
> +        error_report("x-igd-gms is not supported on this device");
> +    } else if (gen < 8) {
> +        if (gms <= 0x10) {
> +            *gmch &= ~(IGD_GMCH_GEN6_GMS_MASK << IGD_GMCH_GEN6_GMS_SHIFT);
> +            *gmch |= gms << IGD_GMCH_GEN6_GMS_SHIFT;
> +            ret = true;
> +        } else {
> +            error_report(QERR_INVALID_PARAMETER_VALUE, "x-igd-gms",
> "0~0x10");
> +        }
> +    } else if (gen == 8) {
> +        if (gms <= 0x40) {
> +            *gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT);
> +            *gmch |= gms << IGD_GMCH_GEN8_GMS_SHIFT;
> +            ret = true;
> +        } else {
> +            error_report(QERR_INVALID_PARAMETER_VALUE, "x-igd-gms",
> "0~0x40");
> +        }
> +    } else {
> +        /* 0x0  to 0x40: 32MB increments starting at 0MB */
> +        /* 0xf0 to 0xfe: 4MB increments starting at 4MB */
> +        if ((gms <= 0x40) || (gms >= 0xf0 && gms <= 0xfe)) {
> +            *gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT);
> +            *gmch |= gms << IGD_GMCH_GEN8_GMS_SHIFT;
> +            ret = true;
> +        } else {
> +            error_report(QERR_INVALID_PARAMETER_VALUE,
> +                         "x-igd-gms", "0~0x40 or 0xf0~0xfe");
> +        }
> +    }
> +
> +    return ret;
> +}
> +
>  #define IGD_GGC_MMIO_OFFSET     0x108040
>  #define IGD_BDSM_MMIO_OFFSET    0x1080C0
>  
> @@ -593,24 +631,9 @@ static bool vfio_pci_igd_config_quirk(VFIOPCIDevice
> *vdev, Error **errp)
>       * 32MiB. This option should only be used when the desired size cannot be
>       * set from DVMT Pre-Allocated option in host BIOS.
>       */
> -    if (vdev->igd_gms) {
> -        if (gen < 8) {
> -            if (vdev->igd_gms <= 0x10) {
> -                gmch &= ~(IGD_GMCH_GEN6_GMS_MASK << IGD_GMCH_GEN6_GMS_SHIFT);
> -                gmch |= vdev->igd_gms << IGD_GMCH_GEN6_GMS_SHIFT;
> -            } else {
> -                error_report(QERR_INVALID_PARAMETER_VALUE,
> -                             "x-igd-gms", "0~0x10");
> -            }
> -        } else {
> -            if (vdev->igd_gms <= 0x40) {
> -                gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT);
> -                gmch |= vdev->igd_gms << IGD_GMCH_GEN8_GMS_SHIFT;
> -            } else {
> -                error_report(QERR_INVALID_PARAMETER_VALUE,
> -                             "x-igd-gms", "0~0x40");
> -            }
> -        }
> +    if (vdev->igd_gms &&
> +        !vfio_pci_igd_override_gms(gen, vdev->igd_gms, &gmch)) {
> +        return false;
>      }
>  
>      gms_size = igd_stolen_memory_size(gen, gmch);

Reviewed-by: Corvin Köhne <c.koehne@beckhoff.com>


-- 
Kind regards,
Corvin

[PATCH 1/9] vfio/igd: Restrict legacy mode to Gen6-9 devices
[PATCH 2/9] vfio/igd: Always emulate ASLS (OpRegion) register
[PATCH 3/9] vfio/igd: Detect IGD device by OpRegion
[PATCH 4/9] vfio/igd: Check vendor and device ID on GVT-g mdev
[PATCH 5/9] vfio/igd: Check OpRegion support on GVT-g mdev
[PATCH 6/9] vfio/igd: Enable OpRegion by default
[PATCH 7/9] vfio/igd: Allow overriding GMS with 0xf0 to 0xfe on Gen9+
[PATCH 8/9] vfio/igd: Only emulate GGC register when x-igd-gms is set
[PATCH 9/9] vfio/igd: Remove generation limitation for IGD passthrough