[v1] target/riscv: Fix write_misa vs aligned next_pc

[PATCH alternate 0/2] target/riscv: Fix write_misa vs aligned next_pc

Richard Henderson posted 2 patches 6 months, 3 weeks ago

Diff against v1
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20250425165055.807801-1-richard.henderson@linaro.org

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/csr.c                      | 9 ++++++---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++++
2 files changed, 10 insertions(+), 3 deletions(-)

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[PATCH alternate 0/2] target/riscv: Fix write_misa vs aligned next_pc

Posted by Richard Henderson 6 months, 3 weeks ago

This is an alternate, but less exact approach.  It assumes that there
will never be a 16 or 48-bit csr write instruction.  This feels dirtier,
but it's a fair assumption involves much less faff.


r~


Richard Henderson (2):
  target/riscv: Update pc before csrw, csrrw
  target/riscv: Fix write_misa vs aligned next_pc

 target/riscv/csr.c                      | 9 ++++++---
 target/riscv/insn_trans/trans_rvi.c.inc | 4 ++++
 2 files changed, 10 insertions(+), 3 deletions(-)

-- 
2.43.0

Re: [PATCH alternate 0/2] target/riscv: Fix write_misa vs aligned next_pc

Posted by Philippe Mathieu-Daudé 6 months, 3 weeks ago

On 25/4/25 18:50, Richard Henderson wrote:
> This is an alternate, but less exact approach.  It assumes that there
> will never be a 16 or 48-bit csr write instruction.  This feels dirtier,
> but it's a fair assumption involves much less faff.

I prefer the other safer version which properly propagate $ra, which
could be useful for callees.

Re: [PATCH alternate 0/2] target/riscv: Fix write_misa vs aligned next_pc

Posted by Daniel Henrique Barboza 6 months, 3 weeks ago


On 4/25/25 7:35 PM, Philippe Mathieu-Daudé wrote:
> On 25/4/25 18:50, Richard Henderson wrote:
>> This is an alternate, but less exact approach.  It assumes that there
>> will never be a 16 or 48-bit csr write instruction.  This feels dirtier,
>> but it's a fair assumption involves much less faff.
> 
> I prefer the other safer version which properly propagate $ra, which
> could be useful for callees.

Both are fine to me. Alistair can pick the one he likes more.



Thanks,

Daniel