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  3. [PATCH 0/7] target/riscv: Fix write_misa vs aligned next_pc
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[PATCH 2/7] target/riscv: Pass ra to riscv_csrrw_do64

Richard Henderson posted 7 patches 6 months, 3 weeks ago
There is a newer version of this series
[PATCH 2/7] target/riscv: Pass ra to riscv_csrrw_do64
Posted by Richard Henderson 6 months, 3 weeks ago 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/csr.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6f1f69eba6..e9c2f95b6e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -5516,7 +5516,8 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
                                        target_ulong *ret_value,
                                        target_ulong new_value,
-                                       target_ulong write_mask)
+                                       target_ulong write_mask,
+                                       uintptr_t ra)
 {
     RISCVException ret;
     target_ulong old_value = 0;
@@ -5546,7 +5547,7 @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
     if (write_mask) {
         new_value = (old_value & ~write_mask) | (new_value & write_mask);
         if (csr_ops[csrno].write) {
-            ret = csr_ops[csrno].write(env, csrno, new_value, 0);
+            ret = csr_ops[csrno].write(env, csrno, new_value, ra);
             if (ret != RISCV_EXCP_NONE) {
                 return ret;
             }
@@ -5569,7 +5570,7 @@ RISCVException riscv_csrr(CPURISCVState *env, int csrno,
         return ret;
     }
 
-    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
+    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0, 0);
 }
 
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
@@ -5581,7 +5582,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
         return ret;
     }
 
-    return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask);
+    return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, 0);
 }
 
 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
@@ -5647,9 +5648,7 @@ RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
      * accesses
      */
     target_ulong old_value;
-    ret = riscv_csrrw_do64(env, csrno, &old_value,
-                           (target_ulong)0,
-                           (target_ulong)0);
+    ret = riscv_csrrw_do64(env, csrno, &old_value, 0, 0, 0);
     if (ret == RISCV_EXCP_NONE && ret_value) {
         *ret_value = int128_make64(old_value);
     }
@@ -5681,7 +5680,7 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
     target_ulong old_value;
     ret = riscv_csrrw_do64(env, csrno, &old_value,
                            int128_getlo(new_value),
-                           int128_getlo(write_mask));
+                           int128_getlo(write_mask), 0);
     if (ret == RISCV_EXCP_NONE && ret_value) {
         *ret_value = int128_make64(old_value);
     }
-- 
2.43.0
Re: [PATCH 2/7] target/riscv: Pass ra to riscv_csrrw_do64
Posted by Alistair Francis 6 months, 3 weeks ago 
On Sat, Apr 26, 2025 at 1:25 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 15 +++++++--------
>  1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6f1f69eba6..e9c2f95b6e 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -5516,7 +5516,8 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
>  static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
>                                         target_ulong *ret_value,
>                                         target_ulong new_value,
> -                                       target_ulong write_mask)
> +                                       target_ulong write_mask,
> +                                       uintptr_t ra)
>  {
>      RISCVException ret;
>      target_ulong old_value = 0;
> @@ -5546,7 +5547,7 @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
>      if (write_mask) {
>          new_value = (old_value & ~write_mask) | (new_value & write_mask);
>          if (csr_ops[csrno].write) {
> -            ret = csr_ops[csrno].write(env, csrno, new_value, 0);
> +            ret = csr_ops[csrno].write(env, csrno, new_value, ra);
>              if (ret != RISCV_EXCP_NONE) {
>                  return ret;
>              }
> @@ -5569,7 +5570,7 @@ RISCVException riscv_csrr(CPURISCVState *env, int csrno,
>          return ret;
>      }
>
> -    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
> +    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0, 0);
>  }
>
>  RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
> @@ -5581,7 +5582,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
>          return ret;
>      }
>
> -    return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask);
> +    return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, 0);
>  }
>
>  static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
> @@ -5647,9 +5648,7 @@ RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
>       * accesses
>       */
>      target_ulong old_value;
> -    ret = riscv_csrrw_do64(env, csrno, &old_value,
> -                           (target_ulong)0,
> -                           (target_ulong)0);
> +    ret = riscv_csrrw_do64(env, csrno, &old_value, 0, 0, 0);
>      if (ret == RISCV_EXCP_NONE && ret_value) {
>          *ret_value = int128_make64(old_value);
>      }
> @@ -5681,7 +5680,7 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
>      target_ulong old_value;
>      ret = riscv_csrrw_do64(env, csrno, &old_value,
>                             int128_getlo(new_value),
> -                           int128_getlo(write_mask));
> +                           int128_getlo(write_mask), 0);
>      if (ret == RISCV_EXCP_NONE && ret_value) {
>          *ret_value = int128_make64(old_value);
>      }
> --
> 2.43.0
>
>
Re: [PATCH 2/7] target/riscv: Pass ra to riscv_csrrw_do64
Posted by Philippe Mathieu-Daudé 6 months, 3 weeks ago 
On 25/4/25 17:23, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/riscv/csr.c | 15 +++++++--------
>   1 file changed, 7 insertions(+), 8 deletions(-)


> @@ -5647,9 +5648,7 @@ RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
>        * accesses
>        */
>       target_ulong old_value;
> -    ret = riscv_csrrw_do64(env, csrno, &old_value,
> -                           (target_ulong)0,
> -                           (target_ulong)0);
> +    ret = riscv_csrrw_do64(env, csrno, &old_value, 0, 0, 0);

:)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Patchew 2.1-devel-b67e4c2

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