[v4] riscv: Add Kunminghu CPU and platform

[PATCH v4 0/2] riscv: Add Kunminghu CPU and platform

Ran Wang posted 2 patches 6 months, 3 weeks ago

Diff against v5

Only 0 patches received!

There is a newer version of this series

MAINTAINERS                                 |   7 +
configs/devices/riscv64-softmmu/default.mak |   1 +
docs/system/riscv/xiangshan-kunminghu.rst   |  39 ++++
docs/system/target-riscv.rst                |   1 +
hw/riscv/Kconfig                            |   9 +
hw/riscv/meson.build                        |   1 +
hw/riscv/xiangshan_kmh.c                    | 220 ++++++++++++++++++++
include/hw/riscv/xiangshan_kmh.h            |  78 +++++++
target/riscv/cpu-qom.h                      |   1 +
target/riscv/cpu.c                          |  64 ++++++
10 files changed, 421 insertions(+)
create mode 100644 docs/system/riscv/xiangshan-kunminghu.rst
create mode 100644 hw/riscv/xiangshan_kmh.c
create mode 100644 include/hw/riscv/xiangshan_kmh.h

Expand all Fold all

[PATCH v4 0/2] riscv: Add Kunminghu CPU and platform

Posted by Ran Wang 6 months, 3 weeks ago

This serial adds Xiangshan Kunminghu CPU and its FPGA prototype
platform, which include UART, CLINT, IMSIC, and APLIC
devices.

More details can be found at
https://github.com/OpenXiangShan/XiangShan

Patches based on alistair/riscv-to-apply.next

Huang Borong (2):
  target/riscv: Add BOSC's Xiangshan Kunminghu CPU
  hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA
    prototype

 MAINTAINERS                                 |   7 +
 configs/devices/riscv64-softmmu/default.mak |   1 +
 docs/system/riscv/xiangshan-kunminghu.rst   |  39 ++++
 docs/system/target-riscv.rst                |   1 +
 hw/riscv/Kconfig                            |   9 +
 hw/riscv/meson.build                        |   1 +
 hw/riscv/xiangshan_kmh.c                    | 220 ++++++++++++++++++++
 include/hw/riscv/xiangshan_kmh.h            |  78 +++++++
 target/riscv/cpu-qom.h                      |   1 +
 target/riscv/cpu.c                          |  64 ++++++
 10 files changed, 421 insertions(+)
 create mode 100644 docs/system/riscv/xiangshan-kunminghu.rst
 create mode 100644 hw/riscv/xiangshan_kmh.c
 create mode 100644 include/hw/riscv/xiangshan_kmh.h

-- 
2.34.1

Re: [PATCH v4 0/2] riscv: Add Kunminghu CPU and platform

Posted by Alistair Francis 5 months ago

On Fri, Apr 25, 2025 at 10:18 PM Ran Wang <wangran@bosc.ac.cn> wrote:
>
> This serial adds Xiangshan Kunminghu CPU and its FPGA prototype
> platform, which include UART, CLINT, IMSIC, and APLIC
> devices.
>
> More details can be found at
> https://github.com/OpenXiangShan/XiangShan
>
> Patches based on alistair/riscv-to-apply.next
>
> Huang Borong (2):
>   target/riscv: Add BOSC's Xiangshan Kunminghu CPU
>   hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA
>     prototype

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  MAINTAINERS                                 |   7 +
>  configs/devices/riscv64-softmmu/default.mak |   1 +
>  docs/system/riscv/xiangshan-kunminghu.rst   |  39 ++++
>  docs/system/target-riscv.rst                |   1 +
>  hw/riscv/Kconfig                            |   9 +
>  hw/riscv/meson.build                        |   1 +
>  hw/riscv/xiangshan_kmh.c                    | 220 ++++++++++++++++++++
>  include/hw/riscv/xiangshan_kmh.h            |  78 +++++++
>  target/riscv/cpu-qom.h                      |   1 +
>  target/riscv/cpu.c                          |  64 ++++++
>  10 files changed, 421 insertions(+)
>  create mode 100644 docs/system/riscv/xiangshan-kunminghu.rst
>  create mode 100644 hw/riscv/xiangshan_kmh.c
>  create mode 100644 include/hw/riscv/xiangshan_kmh.h
>
> --
> 2.34.1
>

Re: [PATCH v4 0/2] riscv: Add Kunminghu CPU and platform

Posted by Ran Wang 5 months, 4 weeks ago

Hello Alistair,

Could you please comment?

I'd like to know if this version of patch set need any more work.

Thanks & Regards,

Ran

On 2025/4/25 20:17, Ran Wang wrote:
> This serial adds Xiangshan Kunminghu CPU and its FPGA prototype
> platform, which include UART, CLINT, IMSIC, and APLIC
> devices.
> 
> More details can be found at
> https://github.com/OpenXiangShan/XiangShan
> 
> Patches based on alistair/riscv-to-apply.next
> 
> Huang Borong (2):
>    target/riscv: Add BOSC's Xiangshan Kunminghu CPU
>    hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA
>      prototype
> 
>   MAINTAINERS                                 |   7 +
>   configs/devices/riscv64-softmmu/default.mak |   1 +
>   docs/system/riscv/xiangshan-kunminghu.rst   |  39 ++++
>   docs/system/target-riscv.rst                |   1 +
>   hw/riscv/Kconfig                            |   9 +
>   hw/riscv/meson.build                        |   1 +
>   hw/riscv/xiangshan_kmh.c                    | 220 ++++++++++++++++++++
>   include/hw/riscv/xiangshan_kmh.h            |  78 +++++++
>   target/riscv/cpu-qom.h                      |   1 +
>   target/riscv/cpu.c                          |  64 ++++++
>   10 files changed, 421 insertions(+)
>   create mode 100644 docs/system/riscv/xiangshan-kunminghu.rst
>   create mode 100644 hw/riscv/xiangshan_kmh.c
>   create mode 100644 include/hw/riscv/xiangshan_kmh.h
>