Add a new function, so we can change reset vector from platforms.

Signed-off-by: Chao-ying Fu <cfu@mips.com>
Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
---
 target/riscv/cpu.h       | 1 +
 target/riscv/translate.c | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 51e49e03de..6d0acbce80 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -632,6 +632,7 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 
+void cpu_set_exception_base(int vp_index, target_ulong address);
 #include "exec/cpu-all.h"
 
 FIELD(TB_FLAGS, MEM_IDX, 0, 3)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d6651f244f..2b8ddd184f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1433,3 +1433,11 @@ void riscv_translate_init(void)
     load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
                              "load_val");
 }
+
+void cpu_set_exception_base(int vp_index, target_ulong address)
+{
+#ifndef CONFIG_USER_ONLY
+    RISCVCPU *vp = RISCV_CPU(qemu_get_cpu(vp_index));
+    vp->env.resetvec = address;
+#endif
+}
-- 
2.34.1