[v2] hw/misc/aspeed_otp: Introduce OTP memory and integrate with SBC

[PATCH v2 0/3] hw/misc/aspeed_otp: Introduce OTP memory and integrate with SBC

Kane Chen via posted 3 patches 7 months ago

Diff against v3
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20250417030957.2586802-1-kane._5Fchen@aspeedtech.com

Maintainers: "Cédric Le Goater" <clg@kaod.org>, Peter Maydell <peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>, Jamin Lin <jamin_lin@aspeedtech.com>, Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>

There is a newer version of this series

hw/arm/aspeed_ast10x0.c         |  19 +++
hw/arm/aspeed_ast2600.c         |  19 +++
hw/misc/aspeed_otpmem.c         | 217 ++++++++++++++++++++++++++++++++
hw/misc/aspeed_sbc.c            | 155 +++++++++++++++++++++++
hw/misc/meson.build             |   1 +
include/hw/arm/aspeed_soc.h     |   2 +
include/hw/misc/aspeed_otpmem.h |  40 ++++++
include/hw/misc/aspeed_sbc.h    |  15 +++
8 files changed, 468 insertions(+)
create mode 100644 hw/misc/aspeed_otpmem.c
create mode 100644 include/hw/misc/aspeed_otpmem.h

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[PATCH v2 0/3] hw/misc/aspeed_otp: Introduce OTP memory and integrate with SBC

Posted by Kane Chen via 7 months ago

From: Kane-Chen-AS <kane_chen@aspeedtech.com>

Dear reviewers,

This patch series introduces a new model for the ASPEED OTP (One-Time
Programmable) memory and integrates it with the ASPEED Secure Boot
Controller (SBC) and SoC models such as AST1030 and AST2600.

The OTP memory is implemented as a QEMU device (`aspeed.otpmem`) and is
designed to simulate fuse-like behavior using a block backend. Programming
is restricted by irreversible bit-flip rules (e.g., 0->1 or 1->0 depending
on address parity). The memory content is persistent and can be passed via
`-drive id=otpmem`.

The SBC device (`aspeed.sbc`) accesses the OTP device through a QOM link
property. This decouples OTP handling from the SBC logic and allows
future extensibility such as secure configuration or key provisioning.

The SoC integration connects the OTP memory to the SBC and provides
device-tree-style infrastructure for future firmware use.

Any feedback or suggestions are appreciated!

Thanks,  
Kane

---

ChangeLog
---------
v2:
- Separated the OTP memory into a standalone QEMU device (`aspeed.otpmem`)
- Replaced ad-hoc file handling with standard `-drive` backend integration
- Linked OTP to SBC via QOM property for cleaner abstraction
- Improved memory bounds checking and irreversible programming logic

v1:
- Embedded OTP logic in the SBC model and created the backing file internally.

---

Kane-Chen-AS (3):
  hw/misc/aspeed_otp: Add Aspeed OTP memory device model
  hw/misc/aspeed_sbc: Connect Aspeed OTP memory device to SBC controller
  hw/arm: Integrate Aspeed OTP memory into AST10x0 and AST2600 SoCs

 hw/arm/aspeed_ast10x0.c         |  19 +++
 hw/arm/aspeed_ast2600.c         |  19 +++
 hw/misc/aspeed_otpmem.c         | 217 ++++++++++++++++++++++++++++++++
 hw/misc/aspeed_sbc.c            | 155 +++++++++++++++++++++++
 hw/misc/meson.build             |   1 +
 include/hw/arm/aspeed_soc.h     |   2 +
 include/hw/misc/aspeed_otpmem.h |  40 ++++++
 include/hw/misc/aspeed_sbc.h    |  15 +++
 8 files changed, 468 insertions(+)
 create mode 100644 hw/misc/aspeed_otpmem.c
 create mode 100644 include/hw/misc/aspeed_otpmem.h

-- 
2.43.0