On 4/15/25 12:23, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-opc.h | 6 ++---
> tcg/optimize.c | 20 ++++++++---------
> tcg/tcg-op.c | 48 ++++++++++++++++++++--------------------
> tcg/tcg.c | 12 ++++------
> tcg/tci.c | 8 +++----
> docs/devel/tcg-ops.rst | 8 +++----
> tcg/tci/tcg-target.c.inc | 4 ++--
> 7 files changed, 50 insertions(+), 56 deletions(-)
>
> diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
> index cb8c134e94..25fd93eb28 100644
> --- a/include/tcg/tcg-opc.h
> +++ b/include/tcg/tcg-opc.h
> @@ -58,6 +58,8 @@ DEF(or, 1, 2, 0, TCG_OPF_INT)
> DEF(orc, 1, 2, 0, TCG_OPF_INT)
> DEF(rems, 1, 2, 0, TCG_OPF_INT)
> DEF(remu, 1, 2, 0, TCG_OPF_INT)
> +DEF(rotl, 1, 2, 0, TCG_OPF_INT)
> +DEF(rotr, 1, 2, 0, TCG_OPF_INT)
> DEF(sar, 1, 2, 0, TCG_OPF_INT)
> DEF(shl, 1, 2, 0, TCG_OPF_INT)
> DEF(shr, 1, 2, 0, TCG_OPF_INT)
> @@ -77,8 +79,6 @@ DEF(st8_i32, 0, 2, 1, 0)
> DEF(st16_i32, 0, 2, 1, 0)
> DEF(st_i32, 0, 2, 1, 0)
> /* shifts/rotates */
> -DEF(rotl_i32, 1, 2, 0, 0)
> -DEF(rotr_i32, 1, 2, 0, 0)
> DEF(deposit_i32, 1, 2, 2, 0)
> DEF(extract_i32, 1, 1, 2, 0)
> DEF(sextract_i32, 1, 1, 2, 0)
> @@ -115,8 +115,6 @@ DEF(st16_i64, 0, 2, 1, 0)
> DEF(st32_i64, 0, 2, 1, 0)
> DEF(st_i64, 0, 2, 1, 0)
> /* shifts/rotates */
> -DEF(rotl_i64, 1, 2, 0, 0)
> -DEF(rotr_i64, 1, 2, 0, 0)
> DEF(deposit_i64, 1, 2, 2, 0)
> DEF(extract_i64, 1, 1, 2, 0)
> DEF(sextract_i64, 1, 1, 2, 0)
> diff --git a/tcg/optimize.c b/tcg/optimize.c
> index edf5c1c77a..d0a1834536 100644
> --- a/tcg/optimize.c
> +++ b/tcg/optimize.c
> @@ -452,16 +452,16 @@ static uint64_t do_constant_folding_2(TCGOpcode op, TCGType type,
> }
> return (int64_t)x >> (y & 63);
>
> - case INDEX_op_rotr_i32:
> - return ror32(x, y & 31);
> -
> - case INDEX_op_rotr_i64:
> + case INDEX_op_rotr:
> + if (type == TCG_TYPE_I32) {
> + return ror32(x, y & 31);
> + }
> return ror64(x, y & 63);
>
> - case INDEX_op_rotl_i32:
> - return rol32(x, y & 31);
> -
> - case INDEX_op_rotl_i64:
> + case INDEX_op_rotl:
> + if (type == TCG_TYPE_I32) {
> + return rol32(x, y & 31);
> + }
> return rol64(x, y & 63);
>
> case INDEX_op_not:
> @@ -3013,8 +3013,8 @@ void tcg_optimize(TCGContext *s)
> case INDEX_op_remu:
> done = fold_remainder(&ctx, op);
> break;
> - CASE_OP_32_64(rotl):
> - CASE_OP_32_64(rotr):
> + case INDEX_op_rotl:
> + case INDEX_op_rotr:
> case INDEX_op_sar:
> case INDEX_op_shl:
> case INDEX_op_shr:
> diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
> index 8c8b9d179b..1989d8d12c 100644
> --- a/tcg/tcg-op.c
> +++ b/tcg/tcg-op.c
> @@ -829,12 +829,12 @@ void tcg_gen_ctpop_i32(TCGv_i32 ret, TCGv_i32 arg1)
>
> void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
> {
> - if (tcg_op_supported(INDEX_op_rotl_i32, TCG_TYPE_I32, 0)) {
> - tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
> - } else if (tcg_op_supported(INDEX_op_rotr_i32, TCG_TYPE_I32, 0)) {
> + if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) {
> + tcg_gen_op3_i32(INDEX_op_rotl, ret, arg1, arg2);
> + } else if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I32, 0)) {
> TCGv_i32 t0 = tcg_temp_ebb_new_i32();
> tcg_gen_neg_i32(t0, arg2);
> - tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, t0);
> + tcg_gen_op3_i32(INDEX_op_rotr, ret, arg1, t0);
> tcg_temp_free_i32(t0);
> } else {
> TCGv_i32 t0 = tcg_temp_ebb_new_i32();
> @@ -854,12 +854,12 @@ void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
> /* some cases can be optimized here */
> if (arg2 == 0) {
> tcg_gen_mov_i32(ret, arg1);
> - } else if (tcg_op_supported(INDEX_op_rotl_i32, TCG_TYPE_I32, 0)) {
> + } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) {
> TCGv_i32 t0 = tcg_constant_i32(arg2);
> - tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, t0);
> - } else if (tcg_op_supported(INDEX_op_rotr_i32, TCG_TYPE_I32, 0)) {
> + tcg_gen_op3_i32(INDEX_op_rotl, ret, arg1, t0);
> + } else if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I32, 0)) {
> TCGv_i32 t0 = tcg_constant_i32(32 - arg2);
> - tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, t0);
> + tcg_gen_op3_i32(INDEX_op_rotr, ret, arg1, t0);
> } else {
> TCGv_i32 t0 = tcg_temp_ebb_new_i32();
> TCGv_i32 t1 = tcg_temp_ebb_new_i32();
> @@ -873,12 +873,12 @@ void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
>
> void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
> {
> - if (tcg_op_supported(INDEX_op_rotr_i32, TCG_TYPE_I32, 0)) {
> - tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
> - } else if (tcg_op_supported(INDEX_op_rotl_i32, TCG_TYPE_I32, 0)) {
> + if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I32, 0)) {
> + tcg_gen_op3_i32(INDEX_op_rotr, ret, arg1, arg2);
> + } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) {
> TCGv_i32 t0 = tcg_temp_ebb_new_i32();
> tcg_gen_neg_i32(t0, arg2);
> - tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, t0);
> + tcg_gen_op3_i32(INDEX_op_rotl, ret, arg1, t0);
> tcg_temp_free_i32(t0);
> } else {
> TCGv_i32 t0 = tcg_temp_ebb_new_i32();
> @@ -2441,12 +2441,12 @@ void tcg_gen_ctpop_i64(TCGv_i64 ret, TCGv_i64 arg1)
>
> void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
> {
> - if (tcg_op_supported(INDEX_op_rotl_i64, TCG_TYPE_I64, 0)) {
> - tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
> - } else if (tcg_op_supported(INDEX_op_rotl_i64, TCG_TYPE_I64, 0)) {
> + if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) {
> + tcg_gen_op3_i64(INDEX_op_rotl, ret, arg1, arg2);
> + } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) {
> TCGv_i64 t0 = tcg_temp_ebb_new_i64();
> tcg_gen_neg_i64(t0, arg2);
> - tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, t0);
> + tcg_gen_op3_i64(INDEX_op_rotr, ret, arg1, t0);
> tcg_temp_free_i64(t0);
> } else {
> TCGv_i64 t0 = tcg_temp_ebb_new_i64();
> @@ -2466,12 +2466,12 @@ void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
> /* some cases can be optimized here */
> if (arg2 == 0) {
> tcg_gen_mov_i64(ret, arg1);
> - } else if (tcg_op_supported(INDEX_op_rotl_i64, TCG_TYPE_I64, 0)) {
> + } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) {
> TCGv_i64 t0 = tcg_constant_i64(arg2);
> - tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, t0);
> - } else if (tcg_op_supported(INDEX_op_rotr_i64, TCG_TYPE_I64, 0)) {
> + tcg_gen_op3_i64(INDEX_op_rotl, ret, arg1, t0);
> + } else if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I64, 0)) {
> TCGv_i64 t0 = tcg_constant_i64(64 - arg2);
> - tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, t0);
> + tcg_gen_op3_i64(INDEX_op_rotr, ret, arg1, t0);
> } else {
> TCGv_i64 t0 = tcg_temp_ebb_new_i64();
> TCGv_i64 t1 = tcg_temp_ebb_new_i64();
> @@ -2485,12 +2485,12 @@ void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
>
> void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
> {
> - if (tcg_op_supported(INDEX_op_rotr_i64, TCG_TYPE_I64, 0)) {
> - tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
> - } else if (tcg_op_supported(INDEX_op_rotl_i64, TCG_TYPE_I64, 0)) {
> + if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I64, 0)) {
> + tcg_gen_op3_i64(INDEX_op_rotr, ret, arg1, arg2);
> + } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) {
> TCGv_i64 t0 = tcg_temp_ebb_new_i64();
> tcg_gen_neg_i64(t0, arg2);
> - tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, t0);
> + tcg_gen_op3_i64(INDEX_op_rotl, ret, arg1, t0);
> tcg_temp_free_i64(t0);
> } else {
> TCGv_i64 t0 = tcg_temp_ebb_new_i64();
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 06d91480d0..15c993d2cd 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -1042,10 +1042,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
> OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
> OUTOP(INDEX_op_rems, TCGOutOpBinary, outop_rems),
> OUTOP(INDEX_op_remu, TCGOutOpBinary, outop_remu),
> - OUTOP(INDEX_op_rotl_i32, TCGOutOpBinary, outop_rotl),
> - OUTOP(INDEX_op_rotl_i64, TCGOutOpBinary, outop_rotl),
> - OUTOP(INDEX_op_rotr_i32, TCGOutOpBinary, outop_rotr),
> - OUTOP(INDEX_op_rotr_i64, TCGOutOpBinary, outop_rotr),
> + OUTOP(INDEX_op_rotl, TCGOutOpBinary, outop_rotl),
> + OUTOP(INDEX_op_rotr, TCGOutOpBinary, outop_rotr),
> OUTOP(INDEX_op_sar, TCGOutOpBinary, outop_sar),
> OUTOP(INDEX_op_shl, TCGOutOpBinary, outop_shl),
> OUTOP(INDEX_op_shr, TCGOutOpBinary, outop_shr),
> @@ -5415,10 +5413,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
> case INDEX_op_orc:
> case INDEX_op_rems:
> case INDEX_op_remu:
> - case INDEX_op_rotl_i32:
> - case INDEX_op_rotl_i64:
> - case INDEX_op_rotr_i32:
> - case INDEX_op_rotr_i64:
> + case INDEX_op_rotl:
> + case INDEX_op_rotr:
> case INDEX_op_sar:
> case INDEX_op_shl:
> case INDEX_op_shr:
> diff --git a/tcg/tci.c b/tcg/tci.c
> index 0fb13ff61d..b1ee14e65f 100644
> --- a/tcg/tci.c
> +++ b/tcg/tci.c
> @@ -786,11 +786,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
>
> /* Shift/rotate operations (64 bit). */
>
> - case INDEX_op_rotl_i64:
> + case INDEX_op_rotl:
> tci_args_rrr(insn, &r0, &r1, &r2);
> regs[r0] = rol64(regs[r1], regs[r2] & 63);
> break;
> - case INDEX_op_rotr_i64:
> + case INDEX_op_rotr:
> tci_args_rrr(insn, &r0, &r1, &r2);
> regs[r0] = ror64(regs[r1], regs[r2] & 63);
> break;
> @@ -1066,13 +1066,13 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
> case INDEX_op_orc:
> case INDEX_op_rems:
> case INDEX_op_remu:
> + case INDEX_op_rotl:
> + case INDEX_op_rotr:
> case INDEX_op_sar:
> case INDEX_op_shl:
> case INDEX_op_shr:
> case INDEX_op_sub:
> case INDEX_op_xor:
> - case INDEX_op_rotl_i64:
> - case INDEX_op_rotr_i64:
> case INDEX_op_clz_i32:
> case INDEX_op_clz_i64:
> case INDEX_op_ctz_i32:
> diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst
> index be82fed41a..c3a6499d01 100644
> --- a/docs/devel/tcg-ops.rst
> +++ b/docs/devel/tcg-ops.rst
> @@ -394,15 +394,15 @@ Shifts/Rotates
> - | *t0* = *t1* >> *t2* (signed)
> | Unspecified behavior for negative or out-of-range shifts.
>
> - * - rotl_i32/i64 *t0*, *t1*, *t2*
> + * - rotl *t0*, *t1*, *t2*
>
> - | Rotation of *t2* bits to the left
> - | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
> + | Unspecified behavior for negative or out-of-range shifts.
>
> - * - rotr_i32/i64 *t0*, *t1*, *t2*
> + * - rotr *t0*, *t1*, *t2*
>
> - | Rotation of *t2* bits to the right.
> - | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
> + | Unspecified behavior for negative or out-of-range shifts.
>
>
> Misc
> diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
> index 0a2da3ba47..0d15547c9f 100644
> --- a/tcg/tci/tcg-target.c.inc
> +++ b/tcg/tci/tcg-target.c.inc
> @@ -773,7 +773,7 @@ static void tgen_rotl(TCGContext *s, TCGType type,
> {
> TCGOpcode opc = (type == TCG_TYPE_I32
> ? INDEX_op_tci_rotl32
> - : INDEX_op_rotl_i64);
> + : INDEX_op_rotl);
> tcg_out_op_rrr(s, opc, a0, a1, a2);
> }
>
> @@ -787,7 +787,7 @@ static void tgen_rotr(TCGContext *s, TCGType type,
> {
> TCGOpcode opc = (type == TCG_TYPE_I32
> ? INDEX_op_tci_rotr32
> - : INDEX_op_rotr_i64);
> + : INDEX_op_rotr);
> tcg_out_op_rrr(s, opc, a0, a1, a2);
> }
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>