The model number was mistakenly set to 0x0b (11) in commit ff04bc1ac4.
The correct value is 0x5b. This mistake occurred because the extended
model bits in cpuid[eax=0x1].eax were overlooked, and only the base
model was used.

Using the wrong model number can affect guest behavior. One known issue
is that vPMU (which relies on the model number) may fail to operate
correctly.

This patch corrects the model field by introducing a new vCPU version.

Additionally, it adds a "Preferred CPU models for Zhaoxin x86 hosts"
section in docs/system/cpu-models-x86.rst.inc to recommend the
appropriate Zhaoxin CPU model(s).

Fixes: ff04bc1ac4 ("target/i386: Introduce Zhaoxin Yongfeng CPU model")
Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
---
 docs/system/cpu-models-x86.rst.inc | 17 +++++++++++++++++
 target/i386/cpu.c                  | 12 ++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x86.rst.inc
index 6a770ca835..ba001422e2 100644
--- a/docs/system/cpu-models-x86.rst.inc
+++ b/docs/system/cpu-models-x86.rst.inc
@@ -369,6 +369,23 @@ features are included if using "Host passthrough" or "Host model".
   Note that not all CPU hardware will support this feature.
 
 
+Preferred CPU models for Zhaoxin x86 hosts
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+The following CPU models are preferred for use on Zhaoxin hosts.
+Administrators / applications are recommended to use the CPU model that
+matches the generation of the host CPUs in use. In a deployment with a
+mixture of host CPU models between machines, if live migration
+compatibility is required, use the newest CPU model that is compatible
+across all desired hosts.
+
+Currently, Zhaoxin provides a single CPU model (with potential for more in
+the near future), which has two versions. Among them, version 2 is recommended
+as it resolves several guest runtime issues related to the model field (FMS).
+
+``YongFeng-v2``
+    Zhaoxin KH-40000 Processor (2022)
+
+
 Default x86 CPU models
 ^^^^^^^^^^^^^^^^^^^^^^
 
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1b64ceaaba..3fb1ec62da 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5621,6 +5621,18 @@ static const X86CPUDefinition builtin_x86_defs[] = {
         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
         .xlevel = 0x80000008,
         .model_id = "Zhaoxin YongFeng Processor",
+        .versions = (X86CPUVersionDefinition[]) {
+            { .version = 1 },
+            {
+                .version = 2,
+                .note = "with the correct model number",
+                .props = (PropValue[]) {
+                    { "model", "0x5b" },
+                    { /* end of list */ }
+                }
+            },
+            { /* end of list */ }
+        }
     },
 };
 
-- 
2.34.1

On 15.04.2025 05:45, Ewan Hai wrote:
> The model number was mistakenly set to 0x0b (11) in commit ff04bc1ac4.
> The correct value is 0x5b. This mistake occurred because the extended
> model bits in cpuid[eax=0x1].eax were overlooked, and only the base
> model was used.
> 
> Using the wrong model number can affect guest behavior. One known issue
> is that vPMU (which relies on the model number) may fail to operate
> correctly.
> 
> This patch corrects the model field by introducing a new vCPU version.
> 
> Additionally, it adds a "Preferred CPU models for Zhaoxin x86 hosts"
> section in docs/system/cpu-models-x86.rst.inc to recommend the
> appropriate Zhaoxin CPU model(s).
> 
> Fixes: ff04bc1ac4 ("target/i386: Introduce Zhaoxin Yongfeng CPU model")
> Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
> Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Is it a qemu-stable material (for 10.0.x)?

I'm picking this one up, please let me know if I should not.

Thanks,

/mjt

On 4/24/25 3:25 PM, Michael Tokarev wrote:
> 
> On 15.04.2025 05:45, Ewan Hai wrote:
>> The model number was mistakenly set to 0x0b (11) in commit ff04bc1ac4.
>> The correct value is 0x5b. This mistake occurred because the extended
>> model bits in cpuid[eax=0x1].eax were overlooked, and only the base
>> model was used.
>>
>> Using the wrong model number can affect guest behavior. One known issue
>> is that vPMU (which relies on the model number) may fail to operate
>> correctly.
>>
>> This patch corrects the model field by introducing a new vCPU version.
>>
>> Additionally, it adds a "Preferred CPU models for Zhaoxin x86 hosts"
>> section in docs/system/cpu-models-x86.rst.inc to recommend the
>> appropriate Zhaoxin CPU model(s).
>>
>> Fixes: ff04bc1ac4 ("target/i386: Introduce Zhaoxin Yongfeng CPU model")
>> Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
>> Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
> 
> Is it a qemu-stable material (for 10.0.x)?
> 
> I'm picking this one up, please let me know if I should not.
> 

I'm not sure if this should go into qemu-stable. Maybe Paolo Bonzini or Zhao can 
answer?

On Mon, Apr 14, 2025 at 10:45:44PM -0400, Ewan Hai wrote:
> Date: Mon, 14 Apr 2025 22:45:44 -0400
> From: Ewan Hai <ewanhai-oc@zhaoxin.com>
> Subject: [PATCH v4] target/i386: Fix model number of Zhaoxin YongFeng vCPU
>  template
> X-Mailer: git-send-email 2.34.1
> 
> The model number was mistakenly set to 0x0b (11) in commit ff04bc1ac4.
> The correct value is 0x5b. This mistake occurred because the extended
> model bits in cpuid[eax=0x1].eax were overlooked, and only the base
> model was used.
> 
> Using the wrong model number can affect guest behavior. One known issue
> is that vPMU (which relies on the model number) may fail to operate
> correctly.
> 
> This patch corrects the model field by introducing a new vCPU version.
> 
> Additionally, it adds a "Preferred CPU models for Zhaoxin x86 hosts"
> section in docs/system/cpu-models-x86.rst.inc to recommend the
> appropriate Zhaoxin CPU model(s).
> 
> Fixes: ff04bc1ac4 ("target/i386: Introduce Zhaoxin Yongfeng CPU model")
> Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>

LGTM,

> Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Thanks,
Zhao