[v2] Several sstc extension fixes

[PATCH v2 0/4] Several sstc extension fixes

Posted by Jim Shu 7 months, 1 week ago

This patch series contains several sstc fixes:

(1) Writing to ACLINT mtime should also update the period of S/VS-mode
    timer, just like M-mode timer.
(2) VSTIP bit of $mip CSR should check both M-mode and H-mode STCE.
(3) Writing to STCE bit may enable/disable sstc extension in S/VS-mode,
    which should update the timer and IRQ pending bits.


Jim Shu (4):
  target/riscv: Add the checking into stimecmp write function.
  hw/intc: riscv_aclint: Fix mtime write for sstc extension
  target/riscv: Fix VSTIP bit in sstc extension.
  target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed

 hw/intc/riscv_aclint.c     |  5 +++
 target/riscv/csr.c         | 53 ++++++++++++++++++++++++++++++-
 target/riscv/time_helper.c | 65 ++++++++++++++++++++++++++++++++++++--
 target/riscv/time_helper.h |  1 +
 4 files changed, 121 insertions(+), 3 deletions(-)

-- 
2.17.1

Re: [PATCH v2 0/4] Several sstc extension fixes

Posted by Alistair Francis 6 months ago

On Wed, Apr 9, 2025 at 12:53 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> This patch series contains several sstc fixes:
>
> (1) Writing to ACLINT mtime should also update the period of S/VS-mode
>     timer, just like M-mode timer.
> (2) VSTIP bit of $mip CSR should check both M-mode and H-mode STCE.
> (3) Writing to STCE bit may enable/disable sstc extension in S/VS-mode,
>     which should update the timer and IRQ pending bits.
>
>
> Jim Shu (4):
>   target/riscv: Add the checking into stimecmp write function.
>   hw/intc: riscv_aclint: Fix mtime write for sstc extension
>   target/riscv: Fix VSTIP bit in sstc extension.
>   target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed

Can you please rebase this on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next

Alistair

>
>  hw/intc/riscv_aclint.c     |  5 +++
>  target/riscv/csr.c         | 53 ++++++++++++++++++++++++++++++-
>  target/riscv/time_helper.c | 65 ++++++++++++++++++++++++++++++++++++--
>  target/riscv/time_helper.h |  1 +
>  4 files changed, 121 insertions(+), 3 deletions(-)
>
> --
> 2.17.1
>
>

Re: [PATCH v2 0/4] Several sstc extension fixes

Posted by Jim Shu 7 months, 1 week ago

Sorry, I forgot to write v2 changes in cover-letter.

Changes in v2:
- Remove duplicated code in riscv_timer_stce_changed() function
- Add sstc spec description in the commit log


On Wed, Apr 9, 2025 at 10:51 AM Jim Shu <jim.shu@sifive.com> wrote:
>
> This patch series contains several sstc fixes:
>
> (1) Writing to ACLINT mtime should also update the period of S/VS-mode
>     timer, just like M-mode timer.
> (2) VSTIP bit of $mip CSR should check both M-mode and H-mode STCE.
> (3) Writing to STCE bit may enable/disable sstc extension in S/VS-mode,
>     which should update the timer and IRQ pending bits.
>
>
> Jim Shu (4):
>   target/riscv: Add the checking into stimecmp write function.
>   hw/intc: riscv_aclint: Fix mtime write for sstc extension
>   target/riscv: Fix VSTIP bit in sstc extension.
>   target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed
>
>  hw/intc/riscv_aclint.c     |  5 +++
>  target/riscv/csr.c         | 53 ++++++++++++++++++++++++++++++-
>  target/riscv/time_helper.c | 65 ++++++++++++++++++++++++++++++++++++--
>  target/riscv/time_helper.h |  1 +
>  4 files changed, 121 insertions(+), 3 deletions(-)
>
> --
> 2.17.1
>

Re: [PATCH v2 0/4] Several sstc extension fixes

Posted by Jim Shu 6 months, 2 weeks ago

Hi,

Gentle ping on this patch.

Thanks,
Jim

On Wed, Apr 9, 2025 at 10:58 AM Jim Shu <jim.shu@sifive.com> wrote:
>
> Sorry, I forgot to write v2 changes in cover-letter.
>
> Changes in v2:
> - Remove duplicated code in riscv_timer_stce_changed() function
> - Add sstc spec description in the commit log
>
>
> On Wed, Apr 9, 2025 at 10:51 AM Jim Shu <jim.shu@sifive.com> wrote:
> >
> > This patch series contains several sstc fixes:
> >
> > (1) Writing to ACLINT mtime should also update the period of S/VS-mode
> >     timer, just like M-mode timer.
> > (2) VSTIP bit of $mip CSR should check both M-mode and H-mode STCE.
> > (3) Writing to STCE bit may enable/disable sstc extension in S/VS-mode,
> >     which should update the timer and IRQ pending bits.
> >
> >
> > Jim Shu (4):
> >   target/riscv: Add the checking into stimecmp write function.
> >   hw/intc: riscv_aclint: Fix mtime write for sstc extension
> >   target/riscv: Fix VSTIP bit in sstc extension.
> >   target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed
> >
> >  hw/intc/riscv_aclint.c     |  5 +++
> >  target/riscv/csr.c         | 53 ++++++++++++++++++++++++++++++-
> >  target/riscv/time_helper.c | 65 ++++++++++++++++++++++++++++++++++++--
> >  target/riscv/time_helper.h |  1 +
> >  4 files changed, 121 insertions(+), 3 deletions(-)
> >
> > --
> > 2.17.1
> >