[v3] target/riscv: SATP mode and CPU definition overhaul

[PATCH 21/27] target/riscv: th: make CSR insertion test a bit more intuitive

Posted by Paolo Bonzini 8 months, 2 weeks ago

In preparation for generalizing the custom CSR functionality,
make the test return bool instead of int.  Make the insertion_test
optional, too.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/riscv/th_csr.c | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
index 6c970d4e813..969a9fe3c80 100644
--- a/target/riscv/th_csr.c
+++ b/target/riscv/th_csr.c
@@ -29,7 +29,7 @@
 
 typedef struct {
     int csrno;
-    int (*insertion_test)(RISCVCPU *cpu);
+    bool (*insertion_test)(RISCVCPU *cpu);
     riscv_csr_operations csr_ops;
 } riscv_csr;
 
@@ -42,13 +42,9 @@ static RISCVException smode(CPURISCVState *env, int csrno)
     return RISCV_EXCP_ILLEGAL_INST;
 }
 
-static int test_thead_mvendorid(RISCVCPU *cpu)
+static bool test_thead_mvendorid(RISCVCPU *cpu)
 {
-    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
-        return -1;
-    }
-
-    return 0;
+    return cpu->cfg.mvendorid == THEAD_VENDOR_ID;
 }
 
 static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
@@ -66,13 +62,12 @@ static riscv_csr th_csr_list[] = {
         .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
     }
 };
-
 void th_register_custom_csrs(RISCVCPU *cpu)
 {
     for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
         int csrno = th_csr_list[i].csrno;
         riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
-        if (!th_csr_list[i].insertion_test(cpu)) {
+        if (!th_csr_list[i].insertion_test || th_csr_list[i].insertion_test(cpu)) {
             riscv_set_csr_ops(csrno, csr_ops);
         }
     }
-- 
2.49.0

Re: [PATCH 21/27] target/riscv: th: make CSR insertion test a bit more intuitive

Posted by Alistair Francis 7 months, 4 weeks ago

On Sun, Apr 6, 2025 at 5:03 PM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> In preparation for generalizing the custom CSR functionality,
> make the test return bool instead of int.  Make the insertion_test
> optional, too.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/th_csr.c | 13 ++++---------
>  1 file changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
> index 6c970d4e813..969a9fe3c80 100644
> --- a/target/riscv/th_csr.c
> +++ b/target/riscv/th_csr.c
> @@ -29,7 +29,7 @@
>
>  typedef struct {
>      int csrno;
> -    int (*insertion_test)(RISCVCPU *cpu);
> +    bool (*insertion_test)(RISCVCPU *cpu);
>      riscv_csr_operations csr_ops;
>  } riscv_csr;
>
> @@ -42,13 +42,9 @@ static RISCVException smode(CPURISCVState *env, int csrno)
>      return RISCV_EXCP_ILLEGAL_INST;
>  }
>
> -static int test_thead_mvendorid(RISCVCPU *cpu)
> +static bool test_thead_mvendorid(RISCVCPU *cpu)
>  {
> -    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
> -        return -1;
> -    }
> -
> -    return 0;
> +    return cpu->cfg.mvendorid == THEAD_VENDOR_ID;
>  }
>
>  static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
> @@ -66,13 +62,12 @@ static riscv_csr th_csr_list[] = {
>          .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
>      }
>  };
> -
>  void th_register_custom_csrs(RISCVCPU *cpu)
>  {
>      for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
>          int csrno = th_csr_list[i].csrno;
>          riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
> -        if (!th_csr_list[i].insertion_test(cpu)) {
> +        if (!th_csr_list[i].insertion_test || th_csr_list[i].insertion_test(cpu)) {
>              riscv_set_csr_ops(csrno, csr_ops);
>          }
>      }
> --
> 2.49.0
>