[v3] target/riscv: SATP mode and CPU definition overhaul

[PATCH 12/27] target/riscv: do not make RISCVCPUConfig fields conditional

Posted by Paolo Bonzini 8 months, 2 weeks ago

Avoid the need for #ifdefs in CPU declarations, keeping them
simple.  After all class_data used to be specified for all
emulators, not just system ones.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/riscv/cpu_cfg_fields.h.inc | 2 --
 target/riscv/cpu.c                | 3 ---
 2 files changed, 5 deletions(-)

diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index ef58826b2bc..59f134a4192 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -164,9 +164,7 @@ TYPED_FIELD(uint16_t, cbom_blocksize, 0)
 TYPED_FIELD(uint16_t, cbop_blocksize, 0)
 TYPED_FIELD(uint16_t, cboz_blocksize, 0)
 
-#ifndef CONFIG_USER_ONLY
 TYPED_FIELD(int8_t, max_satp_mode, -1)
-#endif
 
 #undef BOOL_FIELD
 #undef TYPED_FIELD
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 58cc2743a53..2c2a6a4b44a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1486,10 +1486,7 @@ static void riscv_cpu_init(Object *obj)
     cpu->cfg.cbop_blocksize = 64;
     cpu->cfg.cboz_blocksize = 64;
     cpu->env.vext_ver = VEXT_VERSION_1_00_0;
-
-#ifndef CONFIG_USER_ONLY
     cpu->cfg.max_satp_mode = -1;
-#endif /* CONFIG_USER_ONLY */
 }
 
 static void riscv_bare_cpu_init(Object *obj)
-- 
2.49.0

Re: [PATCH 12/27] target/riscv: do not make RISCVCPUConfig fields conditional

Posted by Alistair Francis 8 months, 2 weeks ago

On Sun, Apr 6, 2025 at 5:03 PM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> Avoid the need for #ifdefs in CPU declarations, keeping them
> simple.  After all class_data used to be specified for all
> emulators, not just system ones.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_cfg_fields.h.inc | 2 --
>  target/riscv/cpu.c                | 3 ---
>  2 files changed, 5 deletions(-)
>
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index ef58826b2bc..59f134a4192 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -164,9 +164,7 @@ TYPED_FIELD(uint16_t, cbom_blocksize, 0)
>  TYPED_FIELD(uint16_t, cbop_blocksize, 0)
>  TYPED_FIELD(uint16_t, cboz_blocksize, 0)
>
> -#ifndef CONFIG_USER_ONLY
>  TYPED_FIELD(int8_t, max_satp_mode, -1)
> -#endif
>
>  #undef BOOL_FIELD
>  #undef TYPED_FIELD
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 58cc2743a53..2c2a6a4b44a 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1486,10 +1486,7 @@ static void riscv_cpu_init(Object *obj)
>      cpu->cfg.cbop_blocksize = 64;
>      cpu->cfg.cboz_blocksize = 64;
>      cpu->env.vext_ver = VEXT_VERSION_1_00_0;
> -
> -#ifndef CONFIG_USER_ONLY
>      cpu->cfg.max_satp_mode = -1;
> -#endif /* CONFIG_USER_ONLY */
>  }
>
>  static void riscv_bare_cpu_init(Object *obj)
> --
> 2.49.0
>