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[PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions

Max Chou posted 12 patches 10 months, 2 weeks ago
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
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[PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions
Posted by Max Chou 10 months, 2 weeks ago 
Handle the overlap of source registers with different EEWs.
The vs1 EEW of vrgatherei16.vv is 16.

Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Co-authored-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 70c19c49ae4..4a0c9fbeff3 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3478,6 +3478,7 @@ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
 {
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
+           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, a->vm) &&
            require_align(a->rd, s->lmul) &&
            require_align(a->rs1, s->lmul) &&
            require_align(a->rs2, s->lmul) &&
@@ -3490,6 +3491,7 @@ static bool vrgatherei16_vv_check(DisasContext *s, arg_rmrr *a)
     int8_t emul = MO_16 - s->sew + s->lmul;
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
+           vext_check_input_eew(s, a->rs1, MO_16, a->rs2, s->sew, a->vm) &&
            (emul >= -3 && emul <= 3) &&
            require_align(a->rd, s->lmul) &&
            require_align(a->rs1, emul) &&
@@ -3509,6 +3511,7 @@ static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
 {
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
+           vext_check_input_eew(s, -1, MO_64, a->rs2, s->sew, a->vm) &&
            require_align(a->rd, s->lmul) &&
            require_align(a->rs2, s->lmul) &&
            (a->rd != a->rs2) &&
-- 
2.43.0
Re: [PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions
Posted by Daniel Henrique Barboza 10 months, 1 week ago 

On 3/29/25 11:44 AM, Max Chou wrote:
> Handle the overlap of source registers with different EEWs.
> The vs1 EEW of vrgatherei16.vv is 16.
> 
> Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
> Co-authored-by: Max Chou <max.chou@sifive.com>

Since you're marked as Author you don't need this co-authored-by tag
in your name too.

Same thing for patches 5 to 11.

> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

With the co-authored-by tag removed:

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 70c19c49ae4..4a0c9fbeff3 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3478,6 +3478,7 @@ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
>   {
>       return require_rvv(s) &&
>              vext_check_isa_ill(s) &&
> +           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, a->vm) &&
>              require_align(a->rd, s->lmul) &&
>              require_align(a->rs1, s->lmul) &&
>              require_align(a->rs2, s->lmul) &&
> @@ -3490,6 +3491,7 @@ static bool vrgatherei16_vv_check(DisasContext *s, arg_rmrr *a)
>       int8_t emul = MO_16 - s->sew + s->lmul;
>       return require_rvv(s) &&
>              vext_check_isa_ill(s) &&
> +           vext_check_input_eew(s, a->rs1, MO_16, a->rs2, s->sew, a->vm) &&
>              (emul >= -3 && emul <= 3) &&
>              require_align(a->rd, s->lmul) &&
>              require_align(a->rs1, emul) &&
> @@ -3509,6 +3511,7 @@ static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
>   {
>       return require_rvv(s) &&
>              vext_check_isa_ill(s) &&
> +           vext_check_input_eew(s, -1, MO_64, a->rs2, s->sew, a->vm) &&
>              require_align(a->rd, s->lmul) &&
>              require_align(a->rs2, s->lmul) &&
>              (a->rd != a->rs2) &&
Re: [PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions
Posted by Max Chou 10 months, 1 week ago 
On 2025/4/5 5:14 PM, Daniel Henrique Barboza wrote:
>
>
> On 3/29/25 11:44 AM, Max Chou wrote:
>> Handle the overlap of source registers with different EEWs.
>> The vs1 EEW of vrgatherei16.vv is 16.
>>
>> Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
>> Co-authored-by: Max Chou <max.chou@sifive.com>
>
> Since you're marked as Author you don't need this co-authored-by tag
> in your name too.
>
> Same thing for patches 5 to 11.
Thanks for the suggestion. I'll remove the co-authored-by tag from 
patches 5 to 11 at v3.

Max
>
>> Signed-off-by: Max Chou <max.chou@sifive.com>
>> ---
>
> With the co-authored-by tag removed:
>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>
>>   target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
>> b/target/riscv/insn_trans/trans_rvv.c.inc
>> index 70c19c49ae4..4a0c9fbeff3 100644
>> --- a/target/riscv/insn_trans/trans_rvv.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
>> @@ -3478,6 +3478,7 @@ static bool vrgather_vv_check(DisasContext *s, 
>> arg_rmrr *a)
>>   {
>>       return require_rvv(s) &&
>>              vext_check_isa_ill(s) &&
>> +           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, 
>> a->vm) &&
>>              require_align(a->rd, s->lmul) &&
>>              require_align(a->rs1, s->lmul) &&
>>              require_align(a->rs2, s->lmul) &&
>> @@ -3490,6 +3491,7 @@ static bool vrgatherei16_vv_check(DisasContext 
>> *s, arg_rmrr *a)
>>       int8_t emul = MO_16 - s->sew + s->lmul;
>>       return require_rvv(s) &&
>>              vext_check_isa_ill(s) &&
>> +           vext_check_input_eew(s, a->rs1, MO_16, a->rs2, s->sew, 
>> a->vm) &&
>>              (emul >= -3 && emul <= 3) &&
>>              require_align(a->rd, s->lmul) &&
>>              require_align(a->rs1, emul) &&
>> @@ -3509,6 +3511,7 @@ static bool vrgather_vx_check(DisasContext *s, 
>> arg_rmrr *a)
>>   {
>>       return require_rvv(s) &&
>>              vext_check_isa_ill(s) &&
>> +           vext_check_input_eew(s, -1, MO_64, a->rs2, s->sew, a->vm) &&
>>              require_align(a->rd, s->lmul) &&
>>              require_align(a->rs2, s->lmul) &&
>>              (a->rd != a->rs2) &&
>

Patchew 2.1-devel-b67e4c2

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