[v2] Fix RVV encoding corner cases

[PATCH v2 12/12] target/riscv: Fix the rvv reserved encoding of unmasked instructions

Posted by Max Chou 10 months, 2 weeks ago

According to the v spec, the encodings of vcomoress.vm and vector
mask-register logical instructions with vm=0 are reserved.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn32.decode | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6d1a13c8260..cd23b1f3a9b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -703,14 +703,14 @@ vfredmax_vs     000111 . ..... ..... 001 ..... 1010111 @r_vm
 # Vector widening ordered and unordered float reduction sum
 vfwredusum_vs   110001 . ..... ..... 001 ..... 1010111 @r_vm
 vfwredosum_vs   110011 . ..... ..... 001 ..... 1010111 @r_vm
-vmand_mm        011001 - ..... ..... 010 ..... 1010111 @r
-vmnand_mm       011101 - ..... ..... 010 ..... 1010111 @r
-vmandn_mm       011000 - ..... ..... 010 ..... 1010111 @r
-vmxor_mm        011011 - ..... ..... 010 ..... 1010111 @r
-vmor_mm         011010 - ..... ..... 010 ..... 1010111 @r
-vmnor_mm        011110 - ..... ..... 010 ..... 1010111 @r
-vmorn_mm        011100 - ..... ..... 010 ..... 1010111 @r
-vmxnor_mm       011111 - ..... ..... 010 ..... 1010111 @r
+vmand_mm        011001 1 ..... ..... 010 ..... 1010111 @r
+vmnand_mm       011101 1 ..... ..... 010 ..... 1010111 @r
+vmandn_mm       011000 1 ..... ..... 010 ..... 1010111 @r
+vmxor_mm        011011 1 ..... ..... 010 ..... 1010111 @r
+vmor_mm         011010 1 ..... ..... 010 ..... 1010111 @r
+vmnor_mm        011110 1 ..... ..... 010 ..... 1010111 @r
+vmorn_mm        011100 1 ..... ..... 010 ..... 1010111 @r
+vmxnor_mm       011111 1 ..... ..... 010 ..... 1010111 @r
 vcpop_m         010000 . ..... 10000 010 ..... 1010111 @r2_vm
 vfirst_m        010000 . ..... 10001 010 ..... 1010111 @r2_vm
 vmsbf_m         010100 . ..... 00001 010 ..... 1010111 @r2_vm
@@ -732,7 +732,7 @@ vrgather_vv     001100 . ..... ..... 000 ..... 1010111 @r_vm
 vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
 vrgather_vx     001100 . ..... ..... 100 ..... 1010111 @r_vm
 vrgather_vi     001100 . ..... ..... 011 ..... 1010111 @r_vm
-vcompress_vm    010111 - ..... ..... 010 ..... 1010111 @r
+vcompress_vm    010111 1 ..... ..... 010 ..... 1010111 @r
 vmv1r_v         100111 1 ..... 00000 011 ..... 1010111 @r2rd
 vmv2r_v         100111 1 ..... 00001 011 ..... 1010111 @r2rd
 vmv4r_v         100111 1 ..... 00011 011 ..... 1010111 @r2rd
-- 
2.43.0

Re: [PATCH v2 12/12] target/riscv: Fix the rvv reserved encoding of unmasked instructions

Posted by Daniel Henrique Barboza 10 months, 1 week ago


On 3/29/25 11:44 AM, Max Chou wrote:
> According to the v spec, the encodings of vcomoress.vm and vector
> mask-register logical instructions with vm=0 are reserved.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn32.decode | 18 +++++++++---------
>   1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 6d1a13c8260..cd23b1f3a9b 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -703,14 +703,14 @@ vfredmax_vs     000111 . ..... ..... 001 ..... 1010111 @r_vm
>   # Vector widening ordered and unordered float reduction sum
>   vfwredusum_vs   110001 . ..... ..... 001 ..... 1010111 @r_vm
>   vfwredosum_vs   110011 . ..... ..... 001 ..... 1010111 @r_vm
> -vmand_mm        011001 - ..... ..... 010 ..... 1010111 @r
> -vmnand_mm       011101 - ..... ..... 010 ..... 1010111 @r
> -vmandn_mm       011000 - ..... ..... 010 ..... 1010111 @r
> -vmxor_mm        011011 - ..... ..... 010 ..... 1010111 @r
> -vmor_mm         011010 - ..... ..... 010 ..... 1010111 @r
> -vmnor_mm        011110 - ..... ..... 010 ..... 1010111 @r
> -vmorn_mm        011100 - ..... ..... 010 ..... 1010111 @r
> -vmxnor_mm       011111 - ..... ..... 010 ..... 1010111 @r
> +vmand_mm        011001 1 ..... ..... 010 ..... 1010111 @r
> +vmnand_mm       011101 1 ..... ..... 010 ..... 1010111 @r
> +vmandn_mm       011000 1 ..... ..... 010 ..... 1010111 @r
> +vmxor_mm        011011 1 ..... ..... 010 ..... 1010111 @r
> +vmor_mm         011010 1 ..... ..... 010 ..... 1010111 @r
> +vmnor_mm        011110 1 ..... ..... 010 ..... 1010111 @r
> +vmorn_mm        011100 1 ..... ..... 010 ..... 1010111 @r
> +vmxnor_mm       011111 1 ..... ..... 010 ..... 1010111 @r
>   vcpop_m         010000 . ..... 10000 010 ..... 1010111 @r2_vm
>   vfirst_m        010000 . ..... 10001 010 ..... 1010111 @r2_vm
>   vmsbf_m         010100 . ..... 00001 010 ..... 1010111 @r2_vm
> @@ -732,7 +732,7 @@ vrgather_vv     001100 . ..... ..... 000 ..... 1010111 @r_vm
>   vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
>   vrgather_vx     001100 . ..... ..... 100 ..... 1010111 @r_vm
>   vrgather_vi     001100 . ..... ..... 011 ..... 1010111 @r_vm
> -vcompress_vm    010111 - ..... ..... 010 ..... 1010111 @r
> +vcompress_vm    010111 1 ..... ..... 010 ..... 1010111 @r
>   vmv1r_v         100111 1 ..... 00000 011 ..... 1010111 @r2rd
>   vmv2r_v         100111 1 ..... 00001 011 ..... 1010111 @r2rd
>   vmv4r_v         100111 1 ..... 00011 011 ..... 1010111 @r2rd