docs/system/ppc/powernv.rst | 9 +- hw/ppc/pnv.c | 546 +++++++++++++++++++++++++ hw/ppc/pnv_chiptod.c | 59 +++ hw/ppc/pnv_core.c | 17 + include/hw/ppc/pnv.h | 38 ++ include/hw/ppc/pnv_chip.h | 7 + include/hw/ppc/pnv_chiptod.h | 2 + include/hw/ppc/pnv_xscom.h | 49 +++ tests/functional/test_ppc64_powernv.py | 34 +- 9 files changed, 743 insertions(+), 18 deletions(-)
Overview
============
Add support for Power11 powernv machine type.
As Power11 core is same as Power10, hence much of the code has been reused
from Power10.
Split Powernv11 chip/machine code into commits introducing: chip,machine,xive,phb
This is to try to keep the code smaller in each commit, but can squash the
xive/phb commits into respective chip/machine commit
Power11 PSeries already added in QEMU in:
commit 273db89bcaf4 ("ppc/pseries: Add Power11 cpu type")
Git Tree for Testing
====================
QEMU: https://github.com/adi-g15-ibm/qemu/tree/p11-powernv-v7
Has been tested with following cases:
* '-M powernv' / '-M powernv10' / '-M powernv11'
* '-smp' option tested
skiboot with Power11 support: https://github.com/open-power/skiboot, since
commit 785a5e3
Linux with Power11 support: https://github.com/torvalds/linux, since v6.9-rc1
Changelog
=========
v7:
+ use Power10 models of homer, sbe, occ, psi, lpc. As they are same.
+ switch powernv tests to use buildroot images instead of op-build images
+ add functional test for powernv11
- remove dynamic sysbus device for PHBs, so no more dynamic number of
PHBs in Power11 as it became complex to handle it and not much used
v6 (https://lore.kernel.org/qemu-devel/20250325112319.927190-1-adityag@linux.ibm.com/):
+ make Pnv11Chip's parent as PnvChip, instead of Pnv10Chip
+ rebase on upstream/master
v5 (https://lore.kernel.org/qemu-devel/57ce8d50-db92-44f0-96a9-e1297eea949f@kaod.org/):
+ add chiptod
+ add instance_init for P11 to use P11 models
+ move patch introducing Pnv11Chip to the last
+ update skiboot.lid to skiboot's upstream/master
v4:
+ patch #5: fix memory leak in pnv_chip_power10_quad_realize
- no change in other patches
v3:
+ patch #1: version power11 as power11_v2.0
+ patch #2: split target hw/pseries code into patch #2
+ patch #3,#4: fix regression due to Power10 and Power11 having same PCR
+ patch #5: create pnv_chip_power11_dt_populate and split pnv_chip_power10_common_realize as per review
+ patch #6-#11: no change
- remove commit to make Power11 as default
v2:
+ split powernv patch into homer,lpc,occ,psi,sbe
+ reduce code duplication by reusing power10 code
+ make power11 as default
+ rebase on qemu upstream/master
+ add more information in commit descriptions
+ update docs
+ update skiboot.lid
Aditya Gupta (7):
ppc/pnv: Introduce Pnv11Chip
ppc/pnv: Introduce Power11 PowerNV machine
ppc/pnv: Add XIVE2 controller to Power11
ppc/pnv: Add PHB5 PCIe Host bridge to Power11
ppc/pnv: Add ChipTOD model for Power11
tests/powernv: Switch to buildroot images instead of op-build
tests/powernv: Add PowerNV test for Power11
docs/system/ppc/powernv.rst | 9 +-
hw/ppc/pnv.c | 546 +++++++++++++++++++++++++
hw/ppc/pnv_chiptod.c | 59 +++
hw/ppc/pnv_core.c | 17 +
include/hw/ppc/pnv.h | 38 ++
include/hw/ppc/pnv_chip.h | 7 +
include/hw/ppc/pnv_chiptod.h | 2 +
include/hw/ppc/pnv_xscom.h | 49 +++
tests/functional/test_ppc64_powernv.py | 34 +-
9 files changed, 743 insertions(+), 18 deletions(-)
--
2.49.0
On 3/27/25 21:07, Aditya Gupta wrote:
> Overview
> ============
>
> Add support for Power11 powernv machine type.
>
> As Power11 core is same as Power10, hence much of the code has been reused
> from Power10.
>
> Split Powernv11 chip/machine code into commits introducing: chip,machine,xive,phb
> This is to try to keep the code smaller in each commit, but can squash the
> xive/phb commits into respective chip/machine commit
>
> Power11 PSeries already added in QEMU in:
> commit 273db89bcaf4 ("ppc/pseries: Add Power11 cpu type")
>
> Git Tree for Testing
> ====================
>
> QEMU: https://github.com/adi-g15-ibm/qemu/tree/p11-powernv-v7
>
> Has been tested with following cases:
> * '-M powernv' / '-M powernv10' / '-M powernv11'
> * '-smp' option tested
>
> skiboot with Power11 support: https://github.com/open-power/skiboot, since
> commit 785a5e3
In OPAL, the Power11 "CPU: PXYZ generation processor" string seems
inconsistent with the previous generations :
[ 0.033505806,6] CPU: P8 generation processor
[ 0.072640552,5] PLAT: Detected QEMU POWER8 platform
[ 0.035156993,6] CPU: P9 generation processor
[ 0.062078034,5] PLAT: Detected QEMU POWER9 platform
[ 0.026078226,6] CPU: P10 generation processor
[ 0.044514479,5] PLAT: Detected QEMU POWER10 platform
[ 0.022154632,6] CPU: Power11 generation processor
[ 0.038760508,5] PLAT: Detected QEMU Power11 platform
Thanks,
C.
>
> Linux with Power11 support: https://github.com/torvalds/linux, since v6.9-rc1
>
> Changelog
> =========
> v7:
> + use Power10 models of homer, sbe, occ, psi, lpc. As they are same.
> + switch powernv tests to use buildroot images instead of op-build images
> + add functional test for powernv11
> - remove dynamic sysbus device for PHBs, so no more dynamic number of
> PHBs in Power11 as it became complex to handle it and not much used
>
> v6 (https://lore.kernel.org/qemu-devel/20250325112319.927190-1-adityag@linux.ibm.com/):
> + make Pnv11Chip's parent as PnvChip, instead of Pnv10Chip
> + rebase on upstream/master
>
> v5 (https://lore.kernel.org/qemu-devel/57ce8d50-db92-44f0-96a9-e1297eea949f@kaod.org/):
> + add chiptod
> + add instance_init for P11 to use P11 models
> + move patch introducing Pnv11Chip to the last
> + update skiboot.lid to skiboot's upstream/master
>
> v4:
> + patch #5: fix memory leak in pnv_chip_power10_quad_realize
> - no change in other patches
>
> v3:
> + patch #1: version power11 as power11_v2.0
> + patch #2: split target hw/pseries code into patch #2
> + patch #3,#4: fix regression due to Power10 and Power11 having same PCR
> + patch #5: create pnv_chip_power11_dt_populate and split pnv_chip_power10_common_realize as per review
> + patch #6-#11: no change
> - remove commit to make Power11 as default
>
> v2:
> + split powernv patch into homer,lpc,occ,psi,sbe
> + reduce code duplication by reusing power10 code
> + make power11 as default
> + rebase on qemu upstream/master
> + add more information in commit descriptions
> + update docs
> + update skiboot.lid
>
> Aditya Gupta (7):
> ppc/pnv: Introduce Pnv11Chip
> ppc/pnv: Introduce Power11 PowerNV machine
> ppc/pnv: Add XIVE2 controller to Power11
> ppc/pnv: Add PHB5 PCIe Host bridge to Power11
> ppc/pnv: Add ChipTOD model for Power11
> tests/powernv: Switch to buildroot images instead of op-build
> tests/powernv: Add PowerNV test for Power11
>
> docs/system/ppc/powernv.rst | 9 +-
> hw/ppc/pnv.c | 546 +++++++++++++++++++++++++
> hw/ppc/pnv_chiptod.c | 59 +++
> hw/ppc/pnv_core.c | 17 +
> include/hw/ppc/pnv.h | 38 ++
> include/hw/ppc/pnv_chip.h | 7 +
> include/hw/ppc/pnv_chiptod.h | 2 +
> include/hw/ppc/pnv_xscom.h | 49 +++
> tests/functional/test_ppc64_powernv.py | 34 +-
> 9 files changed, 743 insertions(+), 18 deletions(-)
>
On 25/03/28 09:02AM, Cédric Le Goater wrote:
> On 3/27/25 21:07, Aditya Gupta wrote:
> > <...snip...>
>
> In OPAL, the Power11 "CPU: PXYZ generation processor" string seems
> inconsistent with the previous generations :
Yes, that was intentional due to how we wanted to export it as "Power11"
Quoting mahesh's reply from skiboot list on 6th Feb 2025:
> Power brand wants to export P11 as Power11. 'P' capital reset
> lower
I have handled this difference in the functional test also, where it
will look for "CPU: P10" for powernv10, but "CPU: Power11" for powernv11
Thanks,
- Aditya G
>
> [ 0.033505806,6] CPU: P8 generation processor
> [ 0.072640552,5] PLAT: Detected QEMU POWER8 platform
> [ 0.035156993,6] CPU: P9 generation processor
> [ 0.062078034,5] PLAT: Detected QEMU POWER9 platform
> [ 0.026078226,6] CPU: P10 generation processor
> [ 0.044514479,5] PLAT: Detected QEMU POWER10 platform
> [ 0.022154632,6] CPU: Power11 generation processor
> [ 0.038760508,5] PLAT: Detected QEMU Power11 platform
>
>
> Thanks,
>
> C.
>
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