Add a XIVE2 controller to Power11 chip and machine.
The controller has the same logic as Power10.
Cc: Cédric Le Goater <clg@kaod.org>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
hw/ppc/pnv.c | 132 ++++++++++++++++++++++++++++++++++++++++++-
include/hw/ppc/pnv.h | 18 ++++++
2 files changed, 149 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 3e63b2891279..ae2c1dcd4684 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -972,6 +972,7 @@ static void pnv_chip_power11_pic_print_info(PnvChip *chip, GString *buf)
Pnv11Chip *chip11 = PNV11_CHIP(chip);
pnv_psi_pic_print_info(&chip11->psi, buf);
+ pnv_xive2_pic_print_info(&chip11->xive, buf);
}
/* Always give the first 1GB to chip 0 else we won't boot */
@@ -1481,6 +1482,50 @@ static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
}
+static void pnv_chip_power11_intc_create(PnvChip *chip, PowerPCCPU *cpu,
+ Error **errp)
+{
+ Pnv11Chip *chip11 = PNV11_CHIP(chip);
+ Error *local_err = NULL;
+ Object *obj;
+ PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
+
+ /*
+ * The core creates its interrupt presenter but the XIVE2 interrupt
+ * controller object is initialized afterwards. Hopefully, it's
+ * only used at runtime.
+ */
+ obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip11->xive),
+ &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ pnv_cpu->intc = obj;
+}
+
+static void pnv_chip_power11_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
+{
+ PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
+
+ xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
+}
+
+static void pnv_chip_power11_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
+{
+ PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
+
+ xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
+ pnv_cpu->intc = NULL;
+}
+
+static void pnv_chip_power11_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
+ GString *buf)
+{
+ xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
+}
+
/*
* Allowed core identifiers on a POWER8 Processor Chip :
*
@@ -2334,6 +2379,9 @@ static void pnv_chip_power11_instance_init(Object *obj)
object_initialize_child(obj, "adu", &chip11->adu, TYPE_PNV_ADU);
object_initialize_child(obj, "psi", &chip11->psi, TYPE_PNV11_PSI);
+ object_initialize_child(obj, "xive", &chip11->xive, TYPE_PNV_XIVE2);
+ object_property_add_alias(obj, "xive-fabric", OBJECT(&chip11->xive),
+ "xive-fabric");
object_initialize_child(obj, "lpc", &chip11->lpc, TYPE_PNV11_LPC);
object_initialize_child(obj, "occ", &chip11->occ, TYPE_PNV11_OCC);
object_initialize_child(obj, "sbe", &chip11->sbe, TYPE_PNV11_SBE);
@@ -2405,11 +2453,33 @@ static void pnv_chip_power11_realize(DeviceState *dev, Error **errp)
return;
}
- /* WIP: XIVE added in future patch */
+ /* XIVE2 interrupt controller */
+ object_property_set_int(OBJECT(&chip11->xive), "ic-bar",
+ PNV11_XIVE2_IC_BASE(chip), &error_fatal);
+ object_property_set_int(OBJECT(&chip11->xive), "esb-bar",
+ PNV11_XIVE2_ESB_BASE(chip), &error_fatal);
+ object_property_set_int(OBJECT(&chip11->xive), "end-bar",
+ PNV11_XIVE2_END_BASE(chip), &error_fatal);
+ object_property_set_int(OBJECT(&chip11->xive), "nvpg-bar",
+ PNV11_XIVE2_NVPG_BASE(chip), &error_fatal);
+ object_property_set_int(OBJECT(&chip11->xive), "nvc-bar",
+ PNV11_XIVE2_NVC_BASE(chip), &error_fatal);
+ object_property_set_int(OBJECT(&chip11->xive), "tm-bar",
+ PNV11_XIVE2_TM_BASE(chip), &error_fatal);
+ object_property_set_link(OBJECT(&chip11->xive), "chip", OBJECT(chip),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&chip11->xive), errp)) {
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV11_XSCOM_XIVE2_BASE,
+ &chip11->xive.xscom_regs);
/* Processor Service Interface (PSI) Host Bridge */
object_property_set_int(OBJECT(&chip11->psi), "bar",
PNV11_PSIHB_BASE(chip), &error_fatal);
+ /* PSI can be configured to use 64k ESB pages on POWER11 */
+ object_property_set_int(OBJECT(&chip11->psi), "shift", XIVE_ESB_64K,
+ &error_fatal);
if (!qdev_realize(DEVICE(&chip11->psi), NULL, errp)) {
return;
}
@@ -2604,6 +2674,10 @@ static void pnv_chip_power11_class_init(ObjectClass *klass, void *data)
k->chip_cfam_id = 0x220da04980000000ull; /* P11 DD2.0 (with NX) */
k->cores_mask = POWER11_CORE_MASK;
k->get_pir_tir = pnv_get_pir_tir_p10;
+ k->intc_create = pnv_chip_power11_intc_create;
+ k->intc_reset = pnv_chip_power11_intc_reset;
+ k->intc_destroy = pnv_chip_power11_intc_destroy;
+ k->intc_print_info = pnv_chip_power11_intc_print_info;
k->isa_create = pnv_chip_power11_isa_create;
k->dt_populate = pnv_chip_power11_dt_populate;
k->pic_print_info = pnv_chip_power11_pic_print_info;
@@ -2972,6 +3046,54 @@ static int pnv10_xive_broadcast(XiveFabric *xfb,
return 0;
}
+static int pnv11_xive_match_nvt(XiveFabric *xfb, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool crowd, bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv,
+ XiveTCTXMatch *match)
+{
+ PnvMachineState *pnv = PNV_MACHINE(xfb);
+ int total_count = 0;
+ int i;
+
+ for (i = 0; i < pnv->num_chips; i++) {
+ Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]);
+ XivePresenter *xptr = XIVE_PRESENTER(&chip11->xive);
+ XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
+ int count;
+
+ count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd,
+ cam_ignore, priority, logic_serv, match);
+
+ if (count < 0) {
+ return count;
+ }
+
+ total_count += count;
+ }
+
+ return total_count;
+}
+
+static int pnv11_xive_broadcast(XiveFabric *xfb,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool crowd, bool cam_ignore,
+ uint8_t priority)
+{
+ PnvMachineState *pnv = PNV_MACHINE(xfb);
+ int i;
+
+ for (i = 0; i < pnv->num_chips; i++) {
+ Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]);
+ XivePresenter *xptr = XIVE_PRESENTER(&chip11->xive);
+ XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
+
+ xpc->broadcast(xptr, nvt_blk, nvt_idx, crowd, cam_ignore, priority);
+ }
+ return 0;
+}
+
+
static bool pnv_machine_get_big_core(Object *obj, Error **errp)
{
PnvMachineState *pnv = PNV_MACHINE(obj);
@@ -3149,6 +3271,7 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
+ XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
static const char compat[] = "qemu,powernv11\0ibm,powernv";
pmc->compat = compat;
@@ -3158,6 +3281,9 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, void *data)
pmc->quirk_tb_big_core = true;
pmc->dt_power_mgt = pnv_dt_power_mgt;
+ xfc->match_nvt = pnv11_xive_match_nvt;
+ xfc->broadcast = pnv11_xive_broadcast;
+
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
mc->desc = "IBM PowerNV (Non-Virtualized) Power11";
@@ -3293,6 +3419,10 @@ static const TypeInfo types[] = {
.name = MACHINE_TYPE_NAME("powernv11"),
.parent = TYPE_PNV_MACHINE,
.class_init = pnv_machine_power11_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_XIVE_FABRIC },
+ { },
+ },
},
{
.name = MACHINE_TYPE_NAME("powernv10-rainier"),
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index f0002627bcab..cbdddfc73cd4 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -270,6 +270,24 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
#define PNV11_PSIHB_SIZE PNV10_PSIHB_SIZE
#define PNV11_PSIHB_BASE(chip) PNV10_PSIHB_BASE(chip)
+#define PNV11_XIVE2_IC_SIZE PNV10_XIVE2_IC_SIZE
+#define PNV11_XIVE2_IC_BASE(chip) PNV10_XIVE2_IC_BASE(chip)
+
+#define PNV11_XIVE2_TM_SIZE PNV10_XIVE2_TM_SIZE
+#define PNV11_XIVE2_TM_BASE(chip) PNV10_XIVE2_TM_BASE(chip)
+
+#define PNV11_XIVE2_NVC_SIZE PNV10_XIVE2_NVC_SIZE
+#define PNV11_XIVE2_NVC_BASE(chip) PNV10_XIVE2_NVC_BASE(chip)
+
+#define PNV11_XIVE2_NVPG_SIZE PNV10_XIVE2_NVPG_SIZE
+#define PNV11_XIVE2_NVPG_BASE(chip) PNV10_XIVE2_NVPG_BASE(chip)
+
+#define PNV11_XIVE2_ESB_SIZE PNV10_XIVE2_ESB_SIZE
+#define PNV11_XIVE2_ESB_BASE(chip) PNV10_XIVE2_ESB_BASE(chip)
+
+#define PNV11_XIVE2_END_SIZE PNV10_XIVE2_END_SIZE
+#define PNV11_XIVE2_END_BASE(chip) PNV10_XIVE2_END_BASE(chip)
+
#define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip)
#endif /* PPC_PNV_H */
--
2.49.0
On 3/25/25 12:23, Aditya Gupta wrote:
> Add a XIVE2 controller to Power11 chip and machine.
> The controller has the same logic as Power10.
>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> Cc: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
LGTM,
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> hw/ppc/pnv.c | 132 ++++++++++++++++++++++++++++++++++++++++++-
> include/hw/ppc/pnv.h | 18 ++++++
> 2 files changed, 149 insertions(+), 1 deletion(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 3e63b2891279..ae2c1dcd4684 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -972,6 +972,7 @@ static void pnv_chip_power11_pic_print_info(PnvChip *chip, GString *buf)
> Pnv11Chip *chip11 = PNV11_CHIP(chip);
>
> pnv_psi_pic_print_info(&chip11->psi, buf);
> + pnv_xive2_pic_print_info(&chip11->xive, buf);
> }
>
> /* Always give the first 1GB to chip 0 else we won't boot */
> @@ -1481,6 +1482,50 @@ static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
> xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
> }
>
> +static void pnv_chip_power11_intc_create(PnvChip *chip, PowerPCCPU *cpu,
> + Error **errp)
> +{
> + Pnv11Chip *chip11 = PNV11_CHIP(chip);
> + Error *local_err = NULL;
> + Object *obj;
> + PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
> +
> + /*
> + * The core creates its interrupt presenter but the XIVE2 interrupt
> + * controller object is initialized afterwards. Hopefully, it's
> + * only used at runtime.
> + */
> + obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip11->xive),
> + &local_err);
> + if (local_err) {
> + error_propagate(errp, local_err);
> + return;
> + }
> +
> + pnv_cpu->intc = obj;
> +}
> +
> +static void pnv_chip_power11_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
> +{
> + PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
> +
> + xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
> +}
> +
> +static void pnv_chip_power11_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
> +{
> + PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
> +
> + xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
> + pnv_cpu->intc = NULL;
> +}
> +
> +static void pnv_chip_power11_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
> + GString *buf)
> +{
> + xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
> +}
> +
> /*
> * Allowed core identifiers on a POWER8 Processor Chip :
> *
> @@ -2334,6 +2379,9 @@ static void pnv_chip_power11_instance_init(Object *obj)
>
> object_initialize_child(obj, "adu", &chip11->adu, TYPE_PNV_ADU);
> object_initialize_child(obj, "psi", &chip11->psi, TYPE_PNV11_PSI);
> + object_initialize_child(obj, "xive", &chip11->xive, TYPE_PNV_XIVE2);
> + object_property_add_alias(obj, "xive-fabric", OBJECT(&chip11->xive),
> + "xive-fabric");
> object_initialize_child(obj, "lpc", &chip11->lpc, TYPE_PNV11_LPC);
> object_initialize_child(obj, "occ", &chip11->occ, TYPE_PNV11_OCC);
> object_initialize_child(obj, "sbe", &chip11->sbe, TYPE_PNV11_SBE);
> @@ -2405,11 +2453,33 @@ static void pnv_chip_power11_realize(DeviceState *dev, Error **errp)
> return;
> }
>
> - /* WIP: XIVE added in future patch */
> + /* XIVE2 interrupt controller */
> + object_property_set_int(OBJECT(&chip11->xive), "ic-bar",
> + PNV11_XIVE2_IC_BASE(chip), &error_fatal);
> + object_property_set_int(OBJECT(&chip11->xive), "esb-bar",
> + PNV11_XIVE2_ESB_BASE(chip), &error_fatal);
> + object_property_set_int(OBJECT(&chip11->xive), "end-bar",
> + PNV11_XIVE2_END_BASE(chip), &error_fatal);
> + object_property_set_int(OBJECT(&chip11->xive), "nvpg-bar",
> + PNV11_XIVE2_NVPG_BASE(chip), &error_fatal);
> + object_property_set_int(OBJECT(&chip11->xive), "nvc-bar",
> + PNV11_XIVE2_NVC_BASE(chip), &error_fatal);
> + object_property_set_int(OBJECT(&chip11->xive), "tm-bar",
> + PNV11_XIVE2_TM_BASE(chip), &error_fatal);
> + object_property_set_link(OBJECT(&chip11->xive), "chip", OBJECT(chip),
> + &error_abort);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&chip11->xive), errp)) {
> + return;
> + }
> + pnv_xscom_add_subregion(chip, PNV11_XSCOM_XIVE2_BASE,
> + &chip11->xive.xscom_regs);
>
> /* Processor Service Interface (PSI) Host Bridge */
> object_property_set_int(OBJECT(&chip11->psi), "bar",
> PNV11_PSIHB_BASE(chip), &error_fatal);
> + /* PSI can be configured to use 64k ESB pages on POWER11 */
> + object_property_set_int(OBJECT(&chip11->psi), "shift", XIVE_ESB_64K,
> + &error_fatal);
> if (!qdev_realize(DEVICE(&chip11->psi), NULL, errp)) {
> return;
> }
> @@ -2604,6 +2674,10 @@ static void pnv_chip_power11_class_init(ObjectClass *klass, void *data)
> k->chip_cfam_id = 0x220da04980000000ull; /* P11 DD2.0 (with NX) */
> k->cores_mask = POWER11_CORE_MASK;
> k->get_pir_tir = pnv_get_pir_tir_p10;
> + k->intc_create = pnv_chip_power11_intc_create;
> + k->intc_reset = pnv_chip_power11_intc_reset;
> + k->intc_destroy = pnv_chip_power11_intc_destroy;
> + k->intc_print_info = pnv_chip_power11_intc_print_info;
> k->isa_create = pnv_chip_power11_isa_create;
> k->dt_populate = pnv_chip_power11_dt_populate;
> k->pic_print_info = pnv_chip_power11_pic_print_info;
> @@ -2972,6 +3046,54 @@ static int pnv10_xive_broadcast(XiveFabric *xfb,
> return 0;
> }
>
> +static int pnv11_xive_match_nvt(XiveFabric *xfb, uint8_t format,
> + uint8_t nvt_blk, uint32_t nvt_idx,
> + bool crowd, bool cam_ignore, uint8_t priority,
> + uint32_t logic_serv,
> + XiveTCTXMatch *match)
> +{
> + PnvMachineState *pnv = PNV_MACHINE(xfb);
> + int total_count = 0;
> + int i;
> +
> + for (i = 0; i < pnv->num_chips; i++) {
> + Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]);
> + XivePresenter *xptr = XIVE_PRESENTER(&chip11->xive);
> + XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
> + int count;
> +
> + count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd,
> + cam_ignore, priority, logic_serv, match);
> +
> + if (count < 0) {
> + return count;
> + }
> +
> + total_count += count;
> + }
> +
> + return total_count;
> +}
> +
> +static int pnv11_xive_broadcast(XiveFabric *xfb,
> + uint8_t nvt_blk, uint32_t nvt_idx,
> + bool crowd, bool cam_ignore,
> + uint8_t priority)
> +{
> + PnvMachineState *pnv = PNV_MACHINE(xfb);
> + int i;
> +
> + for (i = 0; i < pnv->num_chips; i++) {
> + Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]);
> + XivePresenter *xptr = XIVE_PRESENTER(&chip11->xive);
> + XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
> +
> + xpc->broadcast(xptr, nvt_blk, nvt_idx, crowd, cam_ignore, priority);
> + }
> + return 0;
> +}
> +
> +
> static bool pnv_machine_get_big_core(Object *obj, Error **errp)
> {
> PnvMachineState *pnv = PNV_MACHINE(obj);
> @@ -3149,6 +3271,7 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, void *data)
> {
> MachineClass *mc = MACHINE_CLASS(oc);
> PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
> + XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
> static const char compat[] = "qemu,powernv11\0ibm,powernv";
>
> pmc->compat = compat;
> @@ -3158,6 +3281,9 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, void *data)
> pmc->quirk_tb_big_core = true;
> pmc->dt_power_mgt = pnv_dt_power_mgt;
>
> + xfc->match_nvt = pnv11_xive_match_nvt;
> + xfc->broadcast = pnv11_xive_broadcast;
> +
> machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
>
> mc->desc = "IBM PowerNV (Non-Virtualized) Power11";
> @@ -3293,6 +3419,10 @@ static const TypeInfo types[] = {
> .name = MACHINE_TYPE_NAME("powernv11"),
> .parent = TYPE_PNV_MACHINE,
> .class_init = pnv_machine_power11_class_init,
> + .interfaces = (InterfaceInfo[]) {
> + { TYPE_XIVE_FABRIC },
> + { },
> + },
> },
> {
> .name = MACHINE_TYPE_NAME("powernv10-rainier"),
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index f0002627bcab..cbdddfc73cd4 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -270,6 +270,24 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
> #define PNV11_PSIHB_SIZE PNV10_PSIHB_SIZE
> #define PNV11_PSIHB_BASE(chip) PNV10_PSIHB_BASE(chip)
>
> +#define PNV11_XIVE2_IC_SIZE PNV10_XIVE2_IC_SIZE
> +#define PNV11_XIVE2_IC_BASE(chip) PNV10_XIVE2_IC_BASE(chip)
> +
> +#define PNV11_XIVE2_TM_SIZE PNV10_XIVE2_TM_SIZE
> +#define PNV11_XIVE2_TM_BASE(chip) PNV10_XIVE2_TM_BASE(chip)
> +
> +#define PNV11_XIVE2_NVC_SIZE PNV10_XIVE2_NVC_SIZE
> +#define PNV11_XIVE2_NVC_BASE(chip) PNV10_XIVE2_NVC_BASE(chip)
> +
> +#define PNV11_XIVE2_NVPG_SIZE PNV10_XIVE2_NVPG_SIZE
> +#define PNV11_XIVE2_NVPG_BASE(chip) PNV10_XIVE2_NVPG_BASE(chip)
> +
> +#define PNV11_XIVE2_ESB_SIZE PNV10_XIVE2_ESB_SIZE
> +#define PNV11_XIVE2_ESB_BASE(chip) PNV10_XIVE2_ESB_BASE(chip)
> +
> +#define PNV11_XIVE2_END_SIZE PNV10_XIVE2_END_SIZE
> +#define PNV11_XIVE2_END_BASE(chip) PNV10_XIVE2_END_BASE(chip)
> +
> #define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip)
>
> #endif /* PPC_PNV_H */
On 25/03/25 22:36, Cédric Le Goater wrote: > On 3/25/25 12:23, Aditya Gupta wrote: >> Add a XIVE2 controller to Power11 chip and machine. >> The controller has the same logic as Power10. >> >> Cc: Cédric Le Goater <clg@kaod.org> >> Cc: Frédéric Barrat <fbarrat@linux.ibm.com> >> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com> >> Cc: Madhavan Srinivasan <maddy@linux.ibm.com> >> Cc: Nicholas Piggin <npiggin@gmail.com> >> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> > > > LGTM, > > > Reviewed-by: Cédric Le Goater <clg@redhat.com> > Thanks for so many reviews and the tag Cédric. - Aditya Gupta > Thanks, > > C. >
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