[PATCH-for-10.1 1/4] target/riscv: Restrict RV128 MTTCG check on system emulation

Philippe Mathieu-Daudé posted 4 patches 1 week, 3 days ago
There is a newer version of this series
[PATCH-for-10.1 1/4] target/riscv: Restrict RV128 MTTCG check on system emulation
Posted by Philippe Mathieu-Daudé 1 week, 3 days ago
Multi-threaded TCG only concerns system emulation.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/tcg/tcg-cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index fb903992faa..60a26acc503 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1050,6 +1050,7 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
         return false;
     }
 
+#ifndef CONFIG_USER_ONLY
     if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
         /* Missing 128-bit aligned atomics */
         error_setg(errp,
@@ -1058,7 +1059,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
         return false;
     }
 
-#ifndef CONFIG_USER_ONLY
     CPURISCVState *env = &cpu->env;
 
     tcg_cflags_set(CPU(cs), CF_PCREL);
-- 
2.47.1


Re: [PATCH-for-10.1 1/4] target/riscv: Restrict RV128 MTTCG check on system emulation
Posted by Richard Henderson 1 week, 1 day ago
On 3/21/25 08:59, Philippe Mathieu-Daudé wrote:
> Multi-threaded TCG only concerns system emulation.

That's not really true.  User emulation simply has no option to
run in a single-threaded context.

I really don't think we should allow RV128 in user-mode at all.
Certainly not until there's a kernel abi for it.


r~


Re: [PATCH-for-10.1 1/4] target/riscv: Restrict RV128 MTTCG check on system emulation
Posted by Pierrick Bouvier 1 week, 3 days ago
On 3/21/25 08:59, Philippe Mathieu-Daudé wrote:
> Multi-threaded TCG only concerns system emulation.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/riscv/tcg/tcg-cpu.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index fb903992faa..60a26acc503 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -1050,6 +1050,7 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
>           return false;
>       }
>   
> +#ifndef CONFIG_USER_ONLY
>       if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
>           /* Missing 128-bit aligned atomics */
>           error_setg(errp,
> @@ -1058,7 +1059,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
>           return false;
>       }
>   
> -#ifndef CONFIG_USER_ONLY
>       CPURISCVState *env = &cpu->env;
>   
>       tcg_cflags_set(CPU(cs), CF_PCREL);

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>