We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled
frontends, otherwise we use a default value of TCG_MO_ALL.
In order to simplify, require the definition for all targets,
defining it for hexagon, m68k, rx, sh4 and tricore.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/hexagon/cpu-param.h | 3 +++
target/m68k/cpu-param.h | 3 +++
target/rx/cpu-param.h | 3 +++
target/sh4/cpu-param.h | 3 +++
target/tricore/cpu-param.h | 3 +++
accel/tcg/translate-all.c | 4 ----
6 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h
index 45ee7b46409..2d57ea6caf9 100644
--- a/target/hexagon/cpu-param.h
+++ b/target/hexagon/cpu-param.h
@@ -23,4 +23,7 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 36
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+/* MTTCG not yet supported: require strict ordering */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h
index 7afbf6d302d..1a909eaa13e 100644
--- a/target/m68k/cpu-param.h
+++ b/target/m68k/cpu-param.h
@@ -17,4 +17,7 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+/* MTTCG not yet supported: require strict ordering */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h
index ef1970a09e9..2ce199164d7 100644
--- a/target/rx/cpu-param.h
+++ b/target/rx/cpu-param.h
@@ -24,4 +24,7 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+/* MTTCG not yet supported: require strict ordering */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h
index 2b6e11dd0ac..1bc90d4695e 100644
--- a/target/sh4/cpu-param.h
+++ b/target/sh4/cpu-param.h
@@ -16,4 +16,7 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+/* MTTCG not yet supported: require strict ordering */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h
index 790242ef3d2..923459370cc 100644
--- a/target/tricore/cpu-param.h
+++ b/target/tricore/cpu-param.h
@@ -12,4 +12,7 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+/* MTTCG not yet supported: require strict ordering */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 82bc16bd535..fb9f83dbba3 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -349,11 +349,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS;
#endif
tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS;
-#ifdef TCG_GUEST_DEFAULT_MO
tcg_ctx->guest_mo = TCG_GUEST_DEFAULT_MO;
-#else
- tcg_ctx->guest_mo = TCG_MO_ALL;
-#endif
restart_translate:
trace_translate_block(tb, pc, tb->tc.ptr);
--
2.47.1
On 3/21/25 05:57, Philippe Mathieu-Daudé wrote: > We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled > frontends, otherwise we use a default value of TCG_MO_ALL. > > In order to simplify, require the definition for all targets, > defining it for hexagon, m68k, rx, sh4 and tricore. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > target/hexagon/cpu-param.h | 3 +++ > target/m68k/cpu-param.h | 3 +++ > target/rx/cpu-param.h | 3 +++ > target/sh4/cpu-param.h | 3 +++ > target/tricore/cpu-param.h | 3 +++ > accel/tcg/translate-all.c | 4 ---- > 6 files changed, 15 insertions(+), 4 deletions(-) > > diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h > index 45ee7b46409..2d57ea6caf9 100644 > --- a/target/hexagon/cpu-param.h > +++ b/target/hexagon/cpu-param.h > @@ -23,4 +23,7 @@ > #define TARGET_PHYS_ADDR_SPACE_BITS 36 > #define TARGET_VIRT_ADDR_SPACE_BITS 32 > > +/* MTTCG not yet supported: require strict ordering */ > +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL > + > #endif > diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h > index 7afbf6d302d..1a909eaa13e 100644 > --- a/target/m68k/cpu-param.h > +++ b/target/m68k/cpu-param.h > @@ -17,4 +17,7 @@ > #define TARGET_PHYS_ADDR_SPACE_BITS 32 > #define TARGET_VIRT_ADDR_SPACE_BITS 32 > > +/* MTTCG not yet supported: require strict ordering */ > +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL > + > #endif > diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h > index ef1970a09e9..2ce199164d7 100644 > --- a/target/rx/cpu-param.h > +++ b/target/rx/cpu-param.h > @@ -24,4 +24,7 @@ > #define TARGET_PHYS_ADDR_SPACE_BITS 32 > #define TARGET_VIRT_ADDR_SPACE_BITS 32 > > +/* MTTCG not yet supported: require strict ordering */ > +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL > + > #endif > diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h > index 2b6e11dd0ac..1bc90d4695e 100644 > --- a/target/sh4/cpu-param.h > +++ b/target/sh4/cpu-param.h > @@ -16,4 +16,7 @@ > # define TARGET_VIRT_ADDR_SPACE_BITS 32 > #endif > > +/* MTTCG not yet supported: require strict ordering */ > +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL > + > #endif > diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h > index 790242ef3d2..923459370cc 100644 > --- a/target/tricore/cpu-param.h > +++ b/target/tricore/cpu-param.h > @@ -12,4 +12,7 @@ > #define TARGET_PHYS_ADDR_SPACE_BITS 32 > #define TARGET_VIRT_ADDR_SPACE_BITS 32 > > +/* MTTCG not yet supported: require strict ordering */ > +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL > + > #endif > diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c > index 82bc16bd535..fb9f83dbba3 100644 > --- a/accel/tcg/translate-all.c > +++ b/accel/tcg/translate-all.c > @@ -349,11 +349,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, > tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS; > #endif > tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS; > -#ifdef TCG_GUEST_DEFAULT_MO > tcg_ctx->guest_mo = TCG_GUEST_DEFAULT_MO; > -#else > - tcg_ctx->guest_mo = TCG_MO_ALL; > -#endif > > restart_translate: > trace_translate_block(tb, pc, tb->tc.ptr); Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
On 3/21/25 05:57, Philippe Mathieu-Daudé wrote: > We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled > frontends, otherwise we use a default value of TCG_MO_ALL. > > In order to simplify, require the definition for all targets, > defining it for hexagon, m68k, rx, sh4 and tricore. > > Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org> > --- > target/hexagon/cpu-param.h | 3 +++ > target/m68k/cpu-param.h | 3 +++ > target/rx/cpu-param.h | 3 +++ > target/sh4/cpu-param.h | 3 +++ > target/tricore/cpu-param.h | 3 +++ > accel/tcg/translate-all.c | 4 ---- > 6 files changed, 15 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 21/03/25, Philippe Mathieu-Daudé wrote: > We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled > frontends, otherwise we use a default value of TCG_MO_ALL. > > In order to simplify, require the definition for all targets, > defining it for hexagon, m68k, rx, sh4 and tricore. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > target/hexagon/cpu-param.h | 3 +++ > target/m68k/cpu-param.h | 3 +++ > target/rx/cpu-param.h | 3 +++ > target/sh4/cpu-param.h | 3 +++ > target/tricore/cpu-param.h | 3 +++ > accel/tcg/translate-all.c | 4 ---- > 6 files changed, 15 insertions(+), 4 deletions(-) Reviewed-by: Anton Johansson <anjo@rev.ng>
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