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[PATCH v1 14/22] test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations

Jamin Lin via posted 22 patches 10 months, 3 weeks ago
There is a newer version of this series
[PATCH v1 14/22] test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations
Posted by Jamin Lin via 10 months, 3 weeks ago 
The digest_addr is set to "src_addr + 0x1000000", where src_addr is the DRAM
base address. However, the value 0x1000000 (16MB) is too large because the
AST1030 does not support DRAM, and its SRAM size is only 768KB.

A range size of 0x1000 (64KB) is sufficient for HACE test cases, as the test
vector size does not exceed 64KB.

Updates:
1. Direct Access Mode
Update digest_addr to "src_addr + 0x1000" in the following functions:
aspeed_test_md5
aspeed_test_sha256
aspeed_test_sha512

2. Scatter-Gather (SG) Mode
Update source address for different SG buffer addresses in the following
functions:
src_addr1 = src_addr + 0x1000
src_addr2 = src_addr + 0x2000
src_addr3 = src_addr + 0x3000
digest_addr = src_addr + 0x4000

aspeed_test_sha256_sg
aspeed_test_sha512_sg

3. ACC Mode Update
Update the SG List start address: src_addr + 0x10000
Update the SG List buffer size to 0x3000 (192KB).

buffer_addr = src_addr + 0x10000
digest_addr = src_addr + 0x40000

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 tests/qtest/aspeed-hace-utils.c | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-utils.c
index 8582847945..8fbbba49c1 100644
--- a/tests/qtest/aspeed-hace-utils.c
+++ b/tests/qtest/aspeed-hace-utils.c
@@ -132,7 +132,7 @@ void aspeed_test_md5(const char *machine, const uint32_t base,
 {
     QTestState *s = qtest_init(machine);
 
-    uint32_t digest_addr = src_addr + 0x01000000;
+    uint32_t digest_addr = src_addr + 0x010000;
     uint8_t digest[16] = {0};
 
     /* Check engine is idle, no busy or irq bits set */
@@ -166,7 +166,7 @@ void aspeed_test_sha256(const char *machine, const uint32_t base,
 {
     QTestState *s = qtest_init(machine);
 
-    const uint32_t digest_addr = src_addr + 0x1000000;
+    const uint32_t digest_addr = src_addr + 0x10000;
     uint8_t digest[32] = {0};
 
     /* Check engine is idle, no busy or irq bits set */
@@ -200,7 +200,7 @@ void aspeed_test_sha512(const char *machine, const uint32_t base,
 {
     QTestState *s = qtest_init(machine);
 
-    const uint32_t digest_addr = src_addr + 0x1000000;
+    const uint32_t digest_addr = src_addr + 0x10000;
     uint8_t digest[64] = {0};
 
     /* Check engine is idle, no busy or irq bits set */
@@ -234,10 +234,10 @@ void aspeed_test_sha256_sg(const char *machine, const uint32_t base,
 {
     QTestState *s = qtest_init(machine);
 
-    const uint32_t src_addr_1 = src_addr + 0x1000000;
-    const uint32_t src_addr_2 = src_addr + 0x2000000;
-    const uint32_t src_addr_3 = src_addr + 0x3000000;
-    const uint32_t digest_addr = src_addr + 0x4000000;
+    const uint32_t src_addr_1 = src_addr + 0x10000;
+    const uint32_t src_addr_2 = src_addr + 0x20000;
+    const uint32_t src_addr_3 = src_addr + 0x30000;
+    const uint32_t digest_addr = src_addr + 0x40000;
     uint8_t digest[32] = {0};
     struct AspeedSgList array[] = {
         {  cpu_to_le32(sizeof(test_vector_sg1)),
@@ -285,10 +285,10 @@ void aspeed_test_sha512_sg(const char *machine, const uint32_t base,
 {
     QTestState *s = qtest_init(machine);
 
-    const uint32_t src_addr_1 = src_addr + 0x1000000;
-    const uint32_t src_addr_2 = src_addr + 0x2000000;
-    const uint32_t src_addr_3 = src_addr + 0x3000000;
-    const uint32_t digest_addr = src_addr + 0x4000000;
+    const uint32_t src_addr_1 = src_addr + 0x10000;
+    const uint32_t src_addr_2 = src_addr + 0x20000;
+    const uint32_t src_addr_3 = src_addr + 0x30000;
+    const uint32_t digest_addr = src_addr + 0x40000;
     uint8_t digest[64] = {0};
     struct AspeedSgList array[] = {
         {  cpu_to_le32(sizeof(test_vector_sg1)),
@@ -336,8 +336,8 @@ void aspeed_test_sha256_accum(const char *machine, const uint32_t base,
 {
     QTestState *s = qtest_init(machine);
 
-    const uint32_t buffer_addr = src_addr + 0x1000000;
-    const uint32_t digest_addr = src_addr + 0x4000000;
+    const uint32_t buffer_addr = src_addr + 0x10000;
+    const uint32_t digest_addr = src_addr + 0x40000;
     uint8_t digest[32] = {0};
     struct AspeedSgList array[] = {
         {  cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST),
@@ -377,8 +377,8 @@ void aspeed_test_sha512_accum(const char *machine, const uint32_t base,
 {
     QTestState *s = qtest_init(machine);
 
-    const uint32_t buffer_addr = src_addr + 0x1000000;
-    const uint32_t digest_addr = src_addr + 0x4000000;
+    const uint32_t buffer_addr = src_addr + 0x10000;
+    const uint32_t digest_addr = src_addr + 0x40000;
     uint8_t digest[64] = {0};
     struct AspeedSgList array[] = {
         {  cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST),
-- 
2.43.0
Re: [PATCH v1 14/22] test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations
Posted by Cédric Le Goater 10 months, 1 week ago 
On 3/21/25 10:26, Jamin Lin wrote:
> The digest_addr is set to "src_addr + 0x1000000", where src_addr is the DRAM
> base address. However, the value 0x1000000 (16MB) is too large because the
> AST1030 does not support DRAM, and its SRAM size is only 768KB.
> 
> A range size of 0x1000 (64KB) is sufficient for HACE test cases, as the test
> vector size does not exceed 64KB.
> 
> Updates:
> 1. Direct Access Mode
> Update digest_addr to "src_addr + 0x1000" in the following functions:

The change does src_addr + 0x10000. Can you please adjust the commit log
or the code ?


Thanks,

C.



> aspeed_test_md5
> aspeed_test_sha256
> aspeed_test_sha512
> 
> 2. Scatter-Gather (SG) Mode
> Update source address for different SG buffer addresses in the following
> functions:
> src_addr1 = src_addr + 0x1000
> src_addr2 = src_addr + 0x2000
> src_addr3 = src_addr + 0x3000
> digest_addr = src_addr + 0x4000
> 
> aspeed_test_sha256_sg
> aspeed_test_sha512_sg
> 
> 3. ACC Mode Update
> Update the SG List start address: src_addr + 0x10000
> Update the SG List buffer size to 0x3000 (192KB).
> 
> buffer_addr = src_addr + 0x10000
> digest_addr = src_addr + 0x40000
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
>   tests/qtest/aspeed-hace-utils.c | 30 +++++++++++++++---------------
>   1 file changed, 15 insertions(+), 15 deletions(-)
> 
> diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-utils.c
> index 8582847945..8fbbba49c1 100644
> --- a/tests/qtest/aspeed-hace-utils.c
> +++ b/tests/qtest/aspeed-hace-utils.c
> @@ -132,7 +132,7 @@ void aspeed_test_md5(const char *machine, const uint32_t base,
>   {
>       QTestState *s = qtest_init(machine);
>   
> -    uint32_t digest_addr = src_addr + 0x01000000;
> +    uint32_t digest_addr = src_addr + 0x010000;
>       uint8_t digest[16] = {0};
>   
>       /* Check engine is idle, no busy or irq bits set */
> @@ -166,7 +166,7 @@ void aspeed_test_sha256(const char *machine, const uint32_t base,
>   {
>       QTestState *s = qtest_init(machine);
>   
> -    const uint32_t digest_addr = src_addr + 0x1000000;
> +    const uint32_t digest_addr = src_addr + 0x10000;
>       uint8_t digest[32] = {0};
>   
>       /* Check engine is idle, no busy or irq bits set */
> @@ -200,7 +200,7 @@ void aspeed_test_sha512(const char *machine, const uint32_t base,
>   {
>       QTestState *s = qtest_init(machine);
>   
> -    const uint32_t digest_addr = src_addr + 0x1000000;
> +    const uint32_t digest_addr = src_addr + 0x10000;
>       uint8_t digest[64] = {0};
>   
>       /* Check engine is idle, no busy or irq bits set */
> @@ -234,10 +234,10 @@ void aspeed_test_sha256_sg(const char *machine, const uint32_t base,
>   {
>       QTestState *s = qtest_init(machine);
>   
> -    const uint32_t src_addr_1 = src_addr + 0x1000000;
> -    const uint32_t src_addr_2 = src_addr + 0x2000000;
> -    const uint32_t src_addr_3 = src_addr + 0x3000000;
> -    const uint32_t digest_addr = src_addr + 0x4000000;
> +    const uint32_t src_addr_1 = src_addr + 0x10000;
> +    const uint32_t src_addr_2 = src_addr + 0x20000;
> +    const uint32_t src_addr_3 = src_addr + 0x30000;
> +    const uint32_t digest_addr = src_addr + 0x40000;
>       uint8_t digest[32] = {0};
>       struct AspeedSgList array[] = {
>           {  cpu_to_le32(sizeof(test_vector_sg1)),
> @@ -285,10 +285,10 @@ void aspeed_test_sha512_sg(const char *machine, const uint32_t base,
>   {
>       QTestState *s = qtest_init(machine);
>   
> -    const uint32_t src_addr_1 = src_addr + 0x1000000;
> -    const uint32_t src_addr_2 = src_addr + 0x2000000;
> -    const uint32_t src_addr_3 = src_addr + 0x3000000;
> -    const uint32_t digest_addr = src_addr + 0x4000000;
> +    const uint32_t src_addr_1 = src_addr + 0x10000;
> +    const uint32_t src_addr_2 = src_addr + 0x20000;
> +    const uint32_t src_addr_3 = src_addr + 0x30000;
> +    const uint32_t digest_addr = src_addr + 0x40000;
>       uint8_t digest[64] = {0};
>       struct AspeedSgList array[] = {
>           {  cpu_to_le32(sizeof(test_vector_sg1)),
> @@ -336,8 +336,8 @@ void aspeed_test_sha256_accum(const char *machine, const uint32_t base,
>   {
>       QTestState *s = qtest_init(machine);
>   
> -    const uint32_t buffer_addr = src_addr + 0x1000000;
> -    const uint32_t digest_addr = src_addr + 0x4000000;
> +    const uint32_t buffer_addr = src_addr + 0x10000;
> +    const uint32_t digest_addr = src_addr + 0x40000;
>       uint8_t digest[32] = {0};
>       struct AspeedSgList array[] = {
>           {  cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST),
> @@ -377,8 +377,8 @@ void aspeed_test_sha512_accum(const char *machine, const uint32_t base,
>   {
>       QTestState *s = qtest_init(machine);
>   
> -    const uint32_t buffer_addr = src_addr + 0x1000000;
> -    const uint32_t digest_addr = src_addr + 0x4000000;
> +    const uint32_t buffer_addr = src_addr + 0x10000;
> +    const uint32_t digest_addr = src_addr + 0x40000;
>       uint8_t digest[64] = {0};
>       struct AspeedSgList array[] = {
>           {  cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST),
RE: [PATCH v1 14/22] test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations
Posted by Jamin Lin 9 months, 1 week ago 
Hi Cédric
> Subject: Re: [PATCH v1 14/22] test/qtest/hace: Adjust test address range for
> AST1030 due to SRAM limitations
> 
> On 3/21/25 10:26, Jamin Lin wrote:
> > The digest_addr is set to "src_addr + 0x1000000", where src_addr is
> > the DRAM base address. However, the value 0x1000000 (16MB) is too
> > large because the
> > AST1030 does not support DRAM, and its SRAM size is only 768KB.
> >
> > A range size of 0x1000 (64KB) is sufficient for HACE test cases, as
> > the test vector size does not exceed 64KB.
> >
> > Updates:
> > 1. Direct Access Mode
> > Update digest_addr to "src_addr + 0x1000" in the following functions:
> 
> The change does src_addr + 0x10000. Can you please adjust the commit log or
> the code ?
> 
Thanks for review. It should be 0x10000(64KB).
I will adjust the commit log.
Thanks-Jamin
> 
> Thanks,
> 
> C.
> 
> 
> 
> > aspeed_test_md5
> > aspeed_test_sha256
> > aspeed_test_sha512
> >
> > 2. Scatter-Gather (SG) Mode
> > Update source address for different SG buffer addresses in the
> > following
> > functions:
> > src_addr1 = src_addr + 0x1000
> > src_addr2 = src_addr + 0x2000
> > src_addr3 = src_addr + 0x3000
> > digest_addr = src_addr + 0x4000
> >
> > aspeed_test_sha256_sg
> > aspeed_test_sha512_sg
> >
> > 3. ACC Mode Update
> > Update the SG List start address: src_addr + 0x10000 Update the SG
> > List buffer size to 0x3000 (192KB).
> >
> > buffer_addr = src_addr + 0x10000
> > digest_addr = src_addr + 0x40000
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> >   tests/qtest/aspeed-hace-utils.c | 30 +++++++++++++++---------------
> >   1 file changed, 15 insertions(+), 15 deletions(-)
> >
> > diff --git a/tests/qtest/aspeed-hace-utils.c
> > b/tests/qtest/aspeed-hace-utils.c index 8582847945..8fbbba49c1 100644
> > --- a/tests/qtest/aspeed-hace-utils.c
> > +++ b/tests/qtest/aspeed-hace-utils.c
> > @@ -132,7 +132,7 @@ void aspeed_test_md5(const char *machine, const
> uint32_t base,
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    uint32_t digest_addr = src_addr + 0x01000000;
> > +    uint32_t digest_addr = src_addr + 0x010000;
> >       uint8_t digest[16] = {0};
> >
> >       /* Check engine is idle, no busy or irq bits set */ @@ -166,7
> > +166,7 @@ void aspeed_test_sha256(const char *machine, const uint32_t
> base,
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    const uint32_t digest_addr = src_addr + 0x1000000;
> > +    const uint32_t digest_addr = src_addr + 0x10000;
> >       uint8_t digest[32] = {0};
> >
> >       /* Check engine is idle, no busy or irq bits set */ @@ -200,7
> > +200,7 @@ void aspeed_test_sha512(const char *machine, const uint32_t
> base,
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    const uint32_t digest_addr = src_addr + 0x1000000;
> > +    const uint32_t digest_addr = src_addr + 0x10000;
> >       uint8_t digest[64] = {0};
> >
> >       /* Check engine is idle, no busy or irq bits set */ @@ -234,10
> > +234,10 @@ void aspeed_test_sha256_sg(const char *machine, const
> uint32_t base,
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    const uint32_t src_addr_1 = src_addr + 0x1000000;
> > -    const uint32_t src_addr_2 = src_addr + 0x2000000;
> > -    const uint32_t src_addr_3 = src_addr + 0x3000000;
> > -    const uint32_t digest_addr = src_addr + 0x4000000;
> > +    const uint32_t src_addr_1 = src_addr + 0x10000;
> > +    const uint32_t src_addr_2 = src_addr + 0x20000;
> > +    const uint32_t src_addr_3 = src_addr + 0x30000;
> > +    const uint32_t digest_addr = src_addr + 0x40000;
> >       uint8_t digest[32] = {0};
> >       struct AspeedSgList array[] = {
> >           {  cpu_to_le32(sizeof(test_vector_sg1)),
> > @@ -285,10 +285,10 @@ void aspeed_test_sha512_sg(const char *machine,
> const uint32_t base,
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    const uint32_t src_addr_1 = src_addr + 0x1000000;
> > -    const uint32_t src_addr_2 = src_addr + 0x2000000;
> > -    const uint32_t src_addr_3 = src_addr + 0x3000000;
> > -    const uint32_t digest_addr = src_addr + 0x4000000;
> > +    const uint32_t src_addr_1 = src_addr + 0x10000;
> > +    const uint32_t src_addr_2 = src_addr + 0x20000;
> > +    const uint32_t src_addr_3 = src_addr + 0x30000;
> > +    const uint32_t digest_addr = src_addr + 0x40000;
> >       uint8_t digest[64] = {0};
> >       struct AspeedSgList array[] = {
> >           {  cpu_to_le32(sizeof(test_vector_sg1)),
> > @@ -336,8 +336,8 @@ void aspeed_test_sha256_accum(const char
> *machine, const uint32_t base,
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    const uint32_t buffer_addr = src_addr + 0x1000000;
> > -    const uint32_t digest_addr = src_addr + 0x4000000;
> > +    const uint32_t buffer_addr = src_addr + 0x10000;
> > +    const uint32_t digest_addr = src_addr + 0x40000;
> >       uint8_t digest[32] = {0};
> >       struct AspeedSgList array[] = {
> >           {  cpu_to_le32(sizeof(test_vector_accum_256) |
> > SG_LIST_LEN_LAST), @@ -377,8 +377,8 @@ void
> aspeed_test_sha512_accum(const char *machine, const uint32_t base,
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    const uint32_t buffer_addr = src_addr + 0x1000000;
> > -    const uint32_t digest_addr = src_addr + 0x4000000;
> > +    const uint32_t buffer_addr = src_addr + 0x10000;
> > +    const uint32_t digest_addr = src_addr + 0x40000;
> >       uint8_t digest[64] = {0};
> >       struct AspeedSgList array[] = {
> >           {  cpu_to_le32(sizeof(test_vector_accum_512) |
> > SG_LIST_LEN_LAST),

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