[v4] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.

[PATCH 0/1 v4] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.

Paolo Savini posted 1 patch 11 months ago

Diff against v1 v1 v2 v3
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20250313152330.398396-1-paolo.savini@embecosm.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/insn_trans/trans_rvv.c.inc | 155 +++++++++++++++++-------
1 file changed, 108 insertions(+), 47 deletions(-)

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[PATCH 0/1 v4] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.

Posted by Paolo Savini 11 months ago

Previous versions:

- RFC v1: https://lore.kernel.org/all/20241218170840.1090473-1-paolo.savini@embecosm.com/
- RFC v2: https://lore.kernel.org/all/20241220153834.16302-1-paolo.savini@embecosm.com/
- RFC v3: https://lore.kernel.org/all/20250122164905.13615-1-paolo.savini@embecosm.com/

Version v4 of this patch brings the following changes:

- removed the host specific conditions so that the behaviour of the emulation
  doesn't depend on the host we are running on.
  The intruduction of this extra complexity is not worth the very marginal
  performance improvement, when the overall performance improves anyway
  considerably without.
- added reviewers contacts (thanks all for reviewing the work).
- changed the header from RFC to PATCH.

Cc: Richard Handerson <richard.henderson@linaro.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Weiwei Li <liwei1518@gmail.com>
Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: Helene Chelin <helene.chelin@embecosm.com>
Cc: Nathan Egge <negge@google.com>
Cc: Max Chou <max.chou@sifive.com>
Cc: Jeremy Bennett <jeremy.bennett@embecosm.com>
Cc: Craig Blackmore <craig.blackmore@embecosm.com>


Paolo Savini (1):
  target/riscv: use tcg ops generation to emulate whole reg rvv
    loads/stores.

 target/riscv/insn_trans/trans_rvv.c.inc | 155 +++++++++++++++++-------
 1 file changed, 108 insertions(+), 47 deletions(-)

-- 
2.34.1

Re: [PATCH 0/1 v4] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.

Posted by Alistair Francis 10 months, 1 week ago

On Fri, Mar 14, 2025 at 1:24 AM Paolo Savini <paolo.savini@embecosm.com> wrote:
>
> Previous versions:
>
> - RFC v1: https://lore.kernel.org/all/20241218170840.1090473-1-paolo.savini@embecosm.com/
> - RFC v2: https://lore.kernel.org/all/20241220153834.16302-1-paolo.savini@embecosm.com/
> - RFC v3: https://lore.kernel.org/all/20250122164905.13615-1-paolo.savini@embecosm.com/
>
> Version v4 of this patch brings the following changes:
>
> - removed the host specific conditions so that the behaviour of the emulation
>   doesn't depend on the host we are running on.
>   The intruduction of this extra complexity is not worth the very marginal
>   performance improvement, when the overall performance improves anyway
>   considerably without.
> - added reviewers contacts (thanks all for reviewing the work).
> - changed the header from RFC to PATCH.
>
> Cc: Richard Handerson <richard.henderson@linaro.org>
> Cc: Palmer Dabbelt <palmer@dabbelt.com>
> Cc: Alistair Francis <alistair.francis@wdc.com>
> Cc: Bin Meng <bmeng.cn@gmail.com>
> Cc: Weiwei Li <liwei1518@gmail.com>
> Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Cc: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
> Cc: Helene Chelin <helene.chelin@embecosm.com>
> Cc: Nathan Egge <negge@google.com>
> Cc: Max Chou <max.chou@sifive.com>
> Cc: Jeremy Bennett <jeremy.bennett@embecosm.com>
> Cc: Craig Blackmore <craig.blackmore@embecosm.com>
>
>
> Paolo Savini (1):
>   target/riscv: use tcg ops generation to emulate whole reg rvv
>     loads/stores.

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/insn_trans/trans_rvv.c.inc | 155 +++++++++++++++++-------
>  1 file changed, 108 insertions(+), 47 deletions(-)
>
> --
> 2.34.1
>