Maps following unimplemented devices in SoC memory
- dpmcu
- iomem
- iomem0
- iomem1
- ltpi
Iomem, Iomem0 and Iomem1 include unimplemented controllers in the
memory ranges 0x0 - 0x1000000, 0x120000000 - 0x121000000 and
0x14000000 - 0x141000000.
For instance:
- USB hub at 0x12010000
- eSPI at 0x14C5000
- PWM at 0x140C0000
DPMCU stands for Display Port MCU controller. LTPI is used to connect
to AST1700.
AST1700 is an I/O expander that supports the DC-SCM 2.1 LTPI protocol.
It provides AST2700 with additional GPIO, UART, I3C, and other
interfaces.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: Iea6c11651c40e341a395b6dbb81975ea2639aebd
---
include/hw/arm/aspeed_soc.h | 6 +++++
hw/arm/aspeed_ast27x0.c | 51 ++++++++++++++++++++++++++++++++-----
2 files changed, 50 insertions(+), 7 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index f899356ed9..c46ec6302d 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -90,6 +90,8 @@ struct AspeedSoCState {
SerialMM uart[ASPEED_UARTS_NUM];
Clock *sysclk;
UnimplementedDeviceState iomem;
+ UnimplementedDeviceState iomem0;
+ UnimplementedDeviceState iomem1;
UnimplementedDeviceState video;
UnimplementedDeviceState emmc_boot_controller;
UnimplementedDeviceState dpmcu;
@@ -97,6 +99,7 @@ struct AspeedSoCState {
UnimplementedDeviceState espi;
UnimplementedDeviceState udc;
UnimplementedDeviceState sgpiom;
+ UnimplementedDeviceState ltpi;
UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
AspeedAPB2OPBState fsi[2];
};
@@ -171,6 +174,9 @@ const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
enum {
ASPEED_DEV_SPI_BOOT,
ASPEED_DEV_IOMEM,
+ ASPEED_DEV_IOMEM0,
+ ASPEED_DEV_IOMEM1,
+ ASPEED_DEV_LTPI,
ASPEED_DEV_UART0,
ASPEED_DEV_UART1,
ASPEED_DEV_UART2,
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index dce7255a2c..a3fe2582f8 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -23,8 +23,16 @@
#include "qobject/qlist.h"
#include "qemu/log.h"
+#define AST2700_SOC_IO_SIZE 0x01000000
+#define AST2700_SOC_IOMEM_SIZE 0x01000000
+#define AST2700_SOC_DPMCU_SIZE 0x00040000
+#define AST2700_SOC_LTPI_SIZE 0x01000000
+
static const hwaddr aspeed_soc_ast2700_memmap[] = {
+ [ASPEED_DEV_IOMEM] = 0x00000000,
[ASPEED_DEV_SRAM] = 0x10000000,
+ [ASPEED_DEV_DPMCU] = 0x11000000,
+ [ASPEED_DEV_IOMEM0] = 0x12000000,
[ASPEED_DEV_HACE] = 0x12070000,
[ASPEED_DEV_EMMC] = 0x12090000,
[ASPEED_DEV_INTC] = 0x12100000,
@@ -36,6 +44,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_TIMER1] = 0x12C10000,
[ASPEED_DEV_SLI] = 0x12C17000,
[ASPEED_DEV_UART4] = 0X12C1A000,
+ [ASPEED_DEV_IOMEM1] = 0x14000000,
[ASPEED_DEV_FMC] = 0x14000000,
[ASPEED_DEV_SPI0] = 0x14010000,
[ASPEED_DEV_SPI1] = 0x14020000,
@@ -68,6 +77,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_UART12] = 0X14C33B00,
[ASPEED_DEV_WDT] = 0x14C37000,
[ASPEED_DEV_SPI_BOOT] = 0x100000000,
+ [ASPEED_DEV_LTPI] = 0x300000000,
[ASPEED_DEV_SDRAM] = 0x400000000,
};
@@ -491,6 +501,16 @@ static void aspeed_soc_ast2700_init(Object *obj)
snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
object_initialize_child(obj, "hace", &s->hace, typename);
+ object_initialize_child(obj, "dpmcu", &s->dpmcu,
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "ltpi", &s->ltpi,
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "iomem", &s->iomem,
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "iomem0", &s->iomem0,
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "iomem1", &s->iomem1,
+ TYPE_UNIMPLEMENTED_DEVICE);
}
/*
@@ -526,8 +546,10 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(gicbusdev, errp)) {
return false;
}
- sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]);
- sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]);
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 0,
+ sc->memmap[ASPEED_GIC_DIST]);
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 1,
+ sc->memmap[ASPEED_GIC_REDIST]);
for (i = 0; i < sc->num_cpus; i++) {
DeviceState *cpudev = DEVICE(&a->cpu[i]);
@@ -876,11 +898,26 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
- create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
- create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
- create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
- create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000);
- create_unimplemented_device("ast2700.io", 0x0, 0x4000000);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu),
+ "aspeed.dpmcu",
+ sc->memmap[ASPEED_DEV_DPMCU],
+ AST2700_SOC_DPMCU_SIZE);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->ltpi),
+ "aspeed.ltpi",
+ sc->memmap[ASPEED_DEV_LTPI],
+ AST2700_SOC_LTPI_SIZE);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem),
+ "aspeed.io",
+ sc->memmap[ASPEED_DEV_IOMEM],
+ AST2700_SOC_IO_SIZE);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem0),
+ "aspeed.iomem0",
+ sc->memmap[ASPEED_DEV_IOMEM0],
+ AST2700_SOC_IOMEM_SIZE);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem1),
+ "aspeed.iomem1",
+ sc->memmap[ASPEED_DEV_IOMEM1],
+ AST2700_SOC_IOMEM_SIZE);
}
static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, void *data)
--
2.34.1Hello Steven,
On 3/13/25 06:40, Steven Lee wrote:
> Maps following unimplemented devices in SoC memory
> - dpmcu
> - iomem
> - iomem0
> - iomem1
> - ltpi
>
> Iomem, Iomem0 and Iomem1 include unimplemented controllers in the
> memory ranges 0x0 - 0x1000000, 0x120000000 - 0x121000000 and
> 0x14000000 - 0x141000000.
>
> For instance:
> - USB hub at 0x12010000
> - eSPI at 0x14C5000
> - PWM at 0x140C0000
>
> DPMCU stands for Display Port MCU controller. LTPI is used to connect
> to AST1700.
> AST1700 is an I/O expander that supports the DC-SCM 2.1 LTPI protocol.
> It provides AST2700 with additional GPIO, UART, I3C, and other
> interfaces.
For your awareness, I keep in the aspeed branch [1] a series
adding I3C support. It was sent by Google in 2023 [2]. In case
you are interested to upstream.
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
[1] https://github.com/legoater/qemu/commits/aspeed-10.0
[2] https://lore.kernel.org/qemu-devel/20230331010131.1412571-1-komlodi@google.com/
>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> Change-Id: Iea6c11651c40e341a395b6dbb81975ea2639aebd
> ---
> include/hw/arm/aspeed_soc.h | 6 +++++
> hw/arm/aspeed_ast27x0.c | 51 ++++++++++++++++++++++++++++++++-----
> 2 files changed, 50 insertions(+), 7 deletions(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index f899356ed9..c46ec6302d 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -90,6 +90,8 @@ struct AspeedSoCState {
> SerialMM uart[ASPEED_UARTS_NUM];
> Clock *sysclk;
> UnimplementedDeviceState iomem;
> + UnimplementedDeviceState iomem0;
> + UnimplementedDeviceState iomem1;
> UnimplementedDeviceState video;
> UnimplementedDeviceState emmc_boot_controller;
> UnimplementedDeviceState dpmcu;
> @@ -97,6 +99,7 @@ struct AspeedSoCState {
> UnimplementedDeviceState espi;
> UnimplementedDeviceState udc;
> UnimplementedDeviceState sgpiom;
> + UnimplementedDeviceState ltpi;
> UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
> AspeedAPB2OPBState fsi[2];
> };
> @@ -171,6 +174,9 @@ const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
> enum {
> ASPEED_DEV_SPI_BOOT,
> ASPEED_DEV_IOMEM,
> + ASPEED_DEV_IOMEM0,
> + ASPEED_DEV_IOMEM1,
> + ASPEED_DEV_LTPI,
> ASPEED_DEV_UART0,
> ASPEED_DEV_UART1,
> ASPEED_DEV_UART2,
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index dce7255a2c..a3fe2582f8 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -23,8 +23,16 @@
> #include "qobject/qlist.h"
> #include "qemu/log.h"
>
> +#define AST2700_SOC_IO_SIZE 0x01000000
> +#define AST2700_SOC_IOMEM_SIZE 0x01000000
> +#define AST2700_SOC_DPMCU_SIZE 0x00040000
> +#define AST2700_SOC_LTPI_SIZE 0x01000000
> +
> static const hwaddr aspeed_soc_ast2700_memmap[] = {
> + [ASPEED_DEV_IOMEM] = 0x00000000,
> [ASPEED_DEV_SRAM] = 0x10000000,
> + [ASPEED_DEV_DPMCU] = 0x11000000,
> + [ASPEED_DEV_IOMEM0] = 0x12000000,
> [ASPEED_DEV_HACE] = 0x12070000,
> [ASPEED_DEV_EMMC] = 0x12090000,
> [ASPEED_DEV_INTC] = 0x12100000,
> @@ -36,6 +44,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_TIMER1] = 0x12C10000,
> [ASPEED_DEV_SLI] = 0x12C17000,
> [ASPEED_DEV_UART4] = 0X12C1A000,
> + [ASPEED_DEV_IOMEM1] = 0x14000000,
> [ASPEED_DEV_FMC] = 0x14000000,
> [ASPEED_DEV_SPI0] = 0x14010000,
> [ASPEED_DEV_SPI1] = 0x14020000,
> @@ -68,6 +77,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_UART12] = 0X14C33B00,
> [ASPEED_DEV_WDT] = 0x14C37000,
> [ASPEED_DEV_SPI_BOOT] = 0x100000000,
> + [ASPEED_DEV_LTPI] = 0x300000000,
> [ASPEED_DEV_SDRAM] = 0x400000000,
> };
>
> @@ -491,6 +501,16 @@ static void aspeed_soc_ast2700_init(Object *obj)
>
> snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
> object_initialize_child(obj, "hace", &s->hace, typename);
> + object_initialize_child(obj, "dpmcu", &s->dpmcu,
> + TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "ltpi", &s->ltpi,
> + TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "iomem", &s->iomem,
> + TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "iomem0", &s->iomem0,
> + TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "iomem1", &s->iomem1,
> + TYPE_UNIMPLEMENTED_DEVICE);
> }
>
> /*
> @@ -526,8 +546,10 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
> if (!sysbus_realize(gicbusdev, errp)) {
> return false;
> }
> - sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]);
> - sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]);
> + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 0,
> + sc->memmap[ASPEED_GIC_DIST]);
> + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 1,
> + sc->memmap[ASPEED_GIC_REDIST]);
>
> for (i = 0; i < sc->num_cpus; i++) {
> DeviceState *cpudev = DEVICE(&a->cpu[i]);
> @@ -876,11 +898,26 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
> aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
>
> - create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
> - create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
> - create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
> - create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000);
> - create_unimplemented_device("ast2700.io", 0x0, 0x4000000);
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu),
> + "aspeed.dpmcu",
> + sc->memmap[ASPEED_DEV_DPMCU],
> + AST2700_SOC_DPMCU_SIZE);
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->ltpi),
> + "aspeed.ltpi",
> + sc->memmap[ASPEED_DEV_LTPI],
> + AST2700_SOC_LTPI_SIZE);
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem),
> + "aspeed.io",
> + sc->memmap[ASPEED_DEV_IOMEM],
> + AST2700_SOC_IO_SIZE);
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem0),
> + "aspeed.iomem0",
> + sc->memmap[ASPEED_DEV_IOMEM0],
> + AST2700_SOC_IOMEM_SIZE);
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem1),
> + "aspeed.iomem1",
> + sc->memmap[ASPEED_DEV_IOMEM1],
> + AST2700_SOC_IOMEM_SIZE);
> }
>
> static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, void *data)
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