Previous version:

- PATCH v1: https://lore.kernel.org/all/20250211182056.412867-1-paolo.savini@embecosm.com/ 

Follwing the suggestion in the following review by Daniel Barboza:

https://lore.kernel.org/all/9be2ecc4-fed3-4774-a921-259f36e23b1b@ventanamicro.com/

we simplified the emulation by tcg nodes of such a complex operation as strided
loads/stores by breaking it into two separate functions.
One function implements the loop that performs the main load/store operation
with the supporting logic to address the vector elements with the right stride
and to fill with ones the inactive elements in the case of a load.
The second function implements the loop that sets to 1 the tail bytes if we
are in a tail agnostic regime.

Cc: Richard Handerson <richard.henderson@linaro.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Weiwei Li <liwei1518@gmail.com>
Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: Helene Chelin <helene.chelin@embecosm.com>
Cc: Nathan Egge <negge@google.com>
Cc: Max Chou <max.chou@sifive.com>
Cc: Jeremy Bennett <jeremy.bennett@embecosm.com>
Cc: Craig Blackmore <craig.blackmore@embecosm.com>


Paolo Savini (1):
  [RISC-V/RVV] Generate strided vector loads/stores with tcg nodes.

 target/riscv/insn_trans/trans_rvv.c.inc | 323 ++++++++++++++++++++----
 1 file changed, 273 insertions(+), 50 deletions(-)

-- 
2.34.1

On Thu, Mar 13, 2025 at 1:57 AM Paolo Savini <paolo.savini@embecosm.com> wrote:
>
> Previous version:
>
> - PATCH v1: https://lore.kernel.org/all/20250211182056.412867-1-paolo.savini@embecosm.com/
>
> Follwing the suggestion in the following review by Daniel Barboza:
>
> https://lore.kernel.org/all/9be2ecc4-fed3-4774-a921-259f36e23b1b@ventanamicro.com/
>
> we simplified the emulation by tcg nodes of such a complex operation as strided
> loads/stores by breaking it into two separate functions.
> One function implements the loop that performs the main load/store operation
> with the supporting logic to address the vector elements with the right stride
> and to fill with ones the inactive elements in the case of a load.
> The second function implements the loop that sets to 1 the tail bytes if we
> are in a tail agnostic regime.
>
> Cc: Richard Handerson <richard.henderson@linaro.org>
> Cc: Palmer Dabbelt <palmer@dabbelt.com>
> Cc: Alistair Francis <alistair.francis@wdc.com>
> Cc: Bin Meng <bmeng.cn@gmail.com>
> Cc: Weiwei Li <liwei1518@gmail.com>
> Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Cc: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
> Cc: Helene Chelin <helene.chelin@embecosm.com>
> Cc: Nathan Egge <negge@google.com>
> Cc: Max Chou <max.chou@sifive.com>
> Cc: Jeremy Bennett <jeremy.bennett@embecosm.com>
> Cc: Craig Blackmore <craig.blackmore@embecosm.com>
>
>
> Paolo Savini (1):
>   [RISC-V/RVV] Generate strided vector loads/stores with tcg nodes.

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/insn_trans/trans_rvv.c.inc | 323 ++++++++++++++++++++----
>  1 file changed, 273 insertions(+), 50 deletions(-)
>
> --
> 2.34.1
>