When IOPMP is enabled, memory access to system memory from devices and
the CPU will be checked by the IOPMP.
The issue of CPU access to non-CPU address space via IOMMU was previously
mentioned by Jim Shu, who provided a patch[1] to fix it. IOPMP also requires
this patch.
You can use a customized QEMU[2] to run bare-metal demo[3] to show IOPMP
functionality. The modifications involve applying patch[1] and adding a simple
DMA device along with a second IOPMP device to the virt machine. These
additional devices are intended to demonstrate more complex scenarios for IOPMP.
[1] accel/tcg: Store section pointer in CPUTLBEntryFull
https://patchew.org/QEMU/20240612081416.29704-1-jim.shu@sifive.com/20240612081416.29704-2-jim.shu@sifive.com/
[2] https://github.com/zhanyangch/qemu/tree/iopmp_patch_test
[3] https://github.com/zhanyangch/iopmp-test
Changes for v11:
- Update specification version number to v0.7, note that the version number is
changed according to the new lifecycle policy, the contents remain almost
the same as previous version(v0.9.2RC3)
- Add IOPMP document (Alistair)
- Fix naming convention (Alistair)
- Remove redundant memory copy and refine length check in
transaction information (Alistair)
- Refine the entry matching in IOPMP for TLB, now it only matches TLB of
current transalted address instead of full transaction (Alistair)
Changes for v10:
- Fix a build error for iopmp_dispatcher
- The mmio size of IOPMP device is calculated based on properties, rather
than relying on a fixed value
Changes for v9:
- Change the specification version to v0.9.2 RC3
- Remove API for configuration CPU IOPMP property (Alistair)
- Add a dispatcher device to forward iopmp transaction information
Changes for v8:
- Support transactions from CPU
- Add an API to set up IOPMP protection for system memory
- Add an API to configure the RISCV CPU to support IOPMP and specify the
CPU's RRID
- Add an API for DMA operation with IOPMP support
- Add SPDX license identifiers to new files (Stefan W.)
- Remove IOPMP PCI interface(pci_setup_iommu) (Zhiwei)
Changes for v7:
- Change the specification version to v0.9.1
- Remove the sps extension
- Remove stall support, transaction information which need requestor device
support.
- Remove iopmp_cascade option for virt machine
- Refine 'addr' range checks switch case (Daniel)
Ethan Chen (8):
hw/core: Add config stream
memory: Introduce memory region fetch operation
system/physmem: Support IOMMU granularity smaller than TARGET_PAGE
size
target/riscv: Add support for IOPMP
hw/misc/riscv_iopmp_txn_info: Add struct for transaction infomation
hw/misc/riscv_iopmp: Add RISC-V IOPMP device
hw/misc/riscv_iopmp_dispatcher: Device for redirect IOPMP transaction
infomation
hw/riscv/virt: Add IOPMP support
accel/tcg/cputlb.c | 29 +-
docs/specs/index.rst | 1 +
docs/specs/riscv-iopmp.rst | 60 +
docs/system/riscv/virt.rst | 9 +
hw/Kconfig | 1 +
hw/core/Kconfig | 3 +
hw/core/meson.build | 2 +-
hw/misc/Kconfig | 4 +
hw/misc/meson.build | 2 +
hw/misc/riscv_iopmp.c | 2157 ++++++++++++++++++++++
hw/misc/riscv_iopmp_dispatcher.c | 139 ++
hw/misc/trace-events | 4 +
hw/riscv/Kconfig | 1 +
hw/riscv/virt.c | 75 +
include/exec/memory.h | 27 +
include/hw/misc/riscv_iopmp.h | 199 ++
include/hw/misc/riscv_iopmp_dispatcher.h | 61 +
include/hw/misc/riscv_iopmp_txn_info.h | 38 +
include/hw/riscv/virt.h | 3 +
system/memory.c | 104 ++
system/physmem.c | 4 +
system/trace-events | 2 +
target/riscv/cpu.c | 3 +
target/riscv/cpu_cfg.h | 2 +
target/riscv/cpu_helper.c | 18 +-
25 files changed, 2938 insertions(+), 10 deletions(-)
create mode 100644 docs/specs/riscv-iopmp.rst
create mode 100644 hw/misc/riscv_iopmp.c
create mode 100644 hw/misc/riscv_iopmp_dispatcher.c
create mode 100644 include/hw/misc/riscv_iopmp.h
create mode 100644 include/hw/misc/riscv_iopmp_dispatcher.h
create mode 100644 include/hw/misc/riscv_iopmp_txn_info.h
--
2.34.1