On 3/11/2025 8:54 PM, Alejandro Jimenez wrote:
> The definitions encoding the maximum Virtual, Physical, and Guest Virtual
> Address sizes supported by the IOMMU are using incorrect offsets i.e. the
> VASize and GVASize offsets are switched.
>
> Cc: qemu-stable@nongnu.org
> Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
> Signed-off-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com>
Good catch. I had read this code but missed to catch this!
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
-Vasant
> ---
> hw/i386/amd_iommu.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
> index 28125130c6..4c708f8d74 100644
> --- a/hw/i386/amd_iommu.h
> +++ b/hw/i386/amd_iommu.h
> @@ -196,9 +196,9 @@
> #define AMDVI_PAGE_SHIFT_4K 12
> #define AMDVI_PAGE_MASK_4K (~((1ULL << AMDVI_PAGE_SHIFT_4K) - 1))
>
> -#define AMDVI_MAX_VA_ADDR (48UL << 5)
> -#define AMDVI_MAX_PH_ADDR (40UL << 8)
> -#define AMDVI_MAX_GVA_ADDR (48UL << 15)
> +#define AMDVI_MAX_GVA_ADDR (48UL << 5)
> +#define AMDVI_MAX_PH_ADDR (40UL << 8)
> +#define AMDVI_MAX_VA_ADDR (48UL << 15)
>
> /* Completion Wait data size */
> #define AMDVI_COMPLETION_DATA_SIZE 8