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[PATCH v8 1/6] target/arm/tcg: increase cache level for cpu=max

Alireza Sanaee via posted 6 patches 11 months ago
There is a newer version of this series
[PATCH v8 1/6] target/arm/tcg: increase cache level for cpu=max
Posted by Alireza Sanaee via 11 months ago 
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function for cpu=max. It introduces three layers of caches and modifies
the cache description registers accordingly.

Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 target/arm/tcg/cpu64.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 29ab0ac79da9..1405506594c2 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1086,6 +1086,19 @@ void aarch64_max_tcg_initfn(Object *obj)
     uint64_t t;
     uint32_t u;
 
+    /*
+     * Expanded cache set
+     */
+    cpu->clidr = 0x8200123; /* 4 4 3 in 3 bit fields */
+    /* 64KB L1 dcache */
+    cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7);
+    /* 64KB L1 icache */
+    cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2);
+    /* 1MB L2 unified cache */
+    cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7);
+    /* 2MB L3 unified cache */
+    cpu->ccsidr[4] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7);
+
     /*
      * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default
      * to because we started with aarch64_a57_initfn(). A 'max' CPU might
-- 
2.34.1
Re: [PATCH v8 1/6] target/arm/tcg: increase cache level for cpu=max
Posted by Eric Auger 10 months, 1 week ago 
Hi Ali,

On 3/10/25 5:23 PM, Alireza Sanaee via wrote:
> This patch addresses cache description in the `aarch64_max_tcg_initfn`
> function for cpu=max. It introduces three layers of caches and modifies
> the cache description registers accordingly.
>
> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>  target/arm/tcg/cpu64.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index 29ab0ac79da9..1405506594c2 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -1086,6 +1086,19 @@ void aarch64_max_tcg_initfn(Object *obj)
>      uint64_t t;
>      uint32_t u;
>  
> +    /*
> +     * Expanded cache set
> +     */
> +    cpu->clidr = 0x8200123; /* 4 4 3 in 3 bit fields */
 /* 4 4 3 in 3 bit fields */ was not obvious to me at the first reading.
I guess it means unified for L2 and L3 (0x4) and separate I&D for L1
> +    /* 64KB L1 dcache */
> +    cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7);
> +    /* 64KB L1 icache */
> +    cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2);
> +    /* 1MB L2 unified cache */
> +    cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7);
> +    /* 2MB L3 unified cache */
> +    cpu->ccsidr[4] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7);
> +
Out of curiosity how did you come up with those values? Is it an
arvbitrary choice?

Thanks

Eric
>      /*
>       * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default
>       * to because we started with aarch64_a57_initfn(). A 'max' CPU might
Re: [PATCH v8 1/6] target/arm/tcg: increase cache level for cpu=max
Posted by Alireza Sanaee via 10 months, 1 week ago 
On Mon, 7 Apr 2025 19:07:29 +0200
Eric Auger <eric.auger@redhat.com> wrote:

Hi Eric,

> Hi Ali,
> 
> On 3/10/25 5:23 PM, Alireza Sanaee via wrote:
> > This patch addresses cache description in the
> > `aarch64_max_tcg_initfn` function for cpu=max. It introduces three
> > layers of caches and modifies the cache description registers
> > accordingly.
> >
> > Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > ---
> >  target/arm/tcg/cpu64.c | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
> >
> > diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> > index 29ab0ac79da9..1405506594c2 100644
> > --- a/target/arm/tcg/cpu64.c
> > +++ b/target/arm/tcg/cpu64.c
> > @@ -1086,6 +1086,19 @@ void aarch64_max_tcg_initfn(Object *obj)
> >      uint64_t t;
> >      uint32_t u;
> >  
> > +    /*
> > +     * Expanded cache set
> > +     */
> > +    cpu->clidr = 0x8200123; /* 4 4 3 in 3 bit fields */  
>  /* 4 4 3 in 3 bit fields */ was not obvious to me at the first
> reading. I guess it means unified for L2 and L3 (0x4) and separate
> I&D for L1
That is correct. It might be a good idea to update this comment.
> > +    /* 64KB L1 dcache */
> > +    cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 *
> > KiB, 7);
> > +    /* 64KB L1 icache */
> > +    cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 *
> > KiB, 2);
> > +    /* 1MB L2 unified cache */
> > +    cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 *
> > MiB, 7);
> > +    /* 2MB L3 unified cache */
> > +    cpu->ccsidr[4] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 *
> > MiB, 7);
> > +  
> Out of curiosity how did you come up with those values? Is it an
> arvbitrary choice?
The numbers are arbitrary. It was important to just have at least three
layers so I can experiment with L3 cache level, as currently we got
three layers in the interface.

Thanks,
Alireza
> 
> Thanks
> 
> Eric
> >      /*
> >       * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would
> > otherwise default
> >       * to because we started with aarch64_a57_initfn(). A 'max'
> > CPU might  
> 
>

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