docs/system/ppc/powernv.rst | 9 +- hw/ppc/pnv.c | 177 ++++++++++++++++++++++++- hw/ppc/pnv_chiptod.c | 37 ++++++ hw/ppc/pnv_core.c | 11 ++ hw/ppc/pnv_homer.c | 8 ++ hw/ppc/pnv_lpc.c | 14 ++ hw/ppc/pnv_occ.c | 14 ++ hw/ppc/pnv_psi.c | 24 ++++ hw/ppc/pnv_sbe.c | 15 +++ include/hw/ppc/pnv.h | 5 + include/hw/ppc/pnv_chip.h | 7 + include/hw/ppc/pnv_chiptod.h | 2 + include/hw/ppc/pnv_core.h | 1 + include/hw/ppc/pnv_homer.h | 3 + include/hw/ppc/pnv_lpc.h | 4 + include/hw/ppc/pnv_occ.h | 2 + include/hw/ppc/pnv_psi.h | 2 +- include/hw/ppc/pnv_sbe.h | 2 + pc-bios/skiboot.lid | Bin 2527328 -> 2527424 bytes 19 files changed, 321 insertions(+), 10 deletions(-)
Overview ============ Add support for Power11 powernv machine type, to emulate PowerNV VMs running on Power11. As Power11 core is same as Power10, hence much of the code has been reused from Power10. And Power10 PNV Chip has been declared as parent of Power11 PNV Chip so that any existing/new functionality can also be reused for Power11. This parent/child hierarchy causes an issue in .instance_init, as parent's instance_init is also called for the child object. Skip initialising child objects in P10's instance init if we have a P11 chip, this prevents initialising same objects twice by p10 and p11 instance inits. Power11 PSeries already added in QEMU in: commit 273db89bcaf4 ("ppc/pseries: Add Power11 cpu type") Git Tree for Testing ==================== QEMU: https://github.com/adi-g15-ibm/qemu/tree/p11-powernv-v5 Has been tested with following cases: * '-M powernv' / '-M powernv10' / '-M powernv11' * '-smp' option tested skiboot with Power11 support: https://github.com/open-power/skiboot, since commit 785a5e3 Linux with Power11 support: https://github.com/torvalds/linux, since v6.9-rc1 Note: Functional test not added now, will add as soon as op-build releases new kernel image with Power11 support Changelog ========= v5: + add chiptod + add instance_init for P11 to use P11 models + move patch introducing Pnv11Chip to the last + update skiboot.lid to skiboot's upstream/master v4: + patch #5: fix memory leak in pnv_chip_power10_quad_realize - no change in other patches v3: + patch #1: version power11 as power11_v2.0 + patch #2: split target hw/pseries code into patch #2 + patch #3,#4: fix regression due to Power10 and Power11 having same PCR + patch #5: create pnv_chip_power11_dt_populate and split pnv_chip_power10_common_realize as per review + patch #6-#11: no change - remove commit to make Power11 as default v2: + split powernv patch into homer,lpc,occ,psi,sbe + reduce code duplication by reusing power10 code + make power11 as default + rebase on qemu upstream/master + add more information in commit descriptions + update docs + update skiboot.lid Aditya Gupta (8): ppc/pnv: Add HOMER for POWER11 ppc/pnv: Add a LPC controller for POWER11 ppc/pnv: Add OCC for Power11 ppc/pnv: Add a PSI bridge model for Power11 ppc/pnv: Add SBE model for Power11 ppc/pnv: Add ChipTOD model for Power11 ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine ppc/pnv: Update skiboot to support Power11 docs/system/ppc/powernv.rst | 9 +- hw/ppc/pnv.c | 177 ++++++++++++++++++++++++- hw/ppc/pnv_chiptod.c | 37 ++++++ hw/ppc/pnv_core.c | 11 ++ hw/ppc/pnv_homer.c | 8 ++ hw/ppc/pnv_lpc.c | 14 ++ hw/ppc/pnv_occ.c | 14 ++ hw/ppc/pnv_psi.c | 24 ++++ hw/ppc/pnv_sbe.c | 15 +++ include/hw/ppc/pnv.h | 5 + include/hw/ppc/pnv_chip.h | 7 + include/hw/ppc/pnv_chiptod.h | 2 + include/hw/ppc/pnv_core.h | 1 + include/hw/ppc/pnv_homer.h | 3 + include/hw/ppc/pnv_lpc.h | 4 + include/hw/ppc/pnv_occ.h | 2 + include/hw/ppc/pnv_psi.h | 2 +- include/hw/ppc/pnv_sbe.h | 2 + pc-bios/skiboot.lid | Bin 2527328 -> 2527424 bytes 19 files changed, 321 insertions(+), 10 deletions(-) -- 2.48.1
Hello Aditya, On 3/8/25 21:51, Aditya Gupta wrote: > Overview > ============ > > Add support for Power11 powernv machine type, to emulate PowerNV VMs > running on Power11. Could you please consider deprecating the POWER8NVL and POWER8E CPUs and associated chips and machines ? I think keeping POWER8 is fine since it has different HW implementation from the following generations. However, the POWER8NVL and POWER8E variants don't add much to QEMU. They were practical at one point for bringup (2014). They are not anymore. This will remove some lpc peculiarities. Thanks, C. > > As Power11 core is same as Power10, hence much of the code has been reused > from Power10. And Power10 PNV Chip has been declared as parent of Power11 > PNV Chip so that any existing/new functionality can also be reused for > Power11. > > This parent/child hierarchy causes an issue in .instance_init, as parent's > instance_init is also called for the child object. Skip initialising child > objects in P10's instance init if we have a P11 chip, this prevents > initialising same objects twice by p10 and p11 instance inits. > > Power11 PSeries already added in QEMU in: > commit 273db89bcaf4 ("ppc/pseries: Add Power11 cpu type") > > Git Tree for Testing > ==================== > > QEMU: https://github.com/adi-g15-ibm/qemu/tree/p11-powernv-v5 > > Has been tested with following cases: > * '-M powernv' / '-M powernv10' / '-M powernv11' > * '-smp' option tested > > skiboot with Power11 support: https://github.com/open-power/skiboot, since > commit 785a5e3 > > Linux with Power11 support: https://github.com/torvalds/linux, since v6.9-rc1 > > Note: Functional test not added now, will add as soon as op-build releases > new kernel image with Power11 support > > Changelog > ========= > v5: > + add chiptod > + add instance_init for P11 to use P11 models > + move patch introducing Pnv11Chip to the last > + update skiboot.lid to skiboot's upstream/master > > v4: > + patch #5: fix memory leak in pnv_chip_power10_quad_realize > - no change in other patches > > v3: > + patch #1: version power11 as power11_v2.0 > + patch #2: split target hw/pseries code into patch #2 > + patch #3,#4: fix regression due to Power10 and Power11 having same PCR > + patch #5: create pnv_chip_power11_dt_populate and split pnv_chip_power10_common_realize as per review > + patch #6-#11: no change > - remove commit to make Power11 as default > > v2: > + split powernv patch into homer,lpc,occ,psi,sbe > + reduce code duplication by reusing power10 code > + make power11 as default > + rebase on qemu upstream/master > + add more information in commit descriptions > + update docs > + update skiboot.lid > > Aditya Gupta (8): > ppc/pnv: Add HOMER for POWER11 > ppc/pnv: Add a LPC controller for POWER11 > ppc/pnv: Add OCC for Power11 > ppc/pnv: Add a PSI bridge model for Power11 > ppc/pnv: Add SBE model for Power11 > ppc/pnv: Add ChipTOD model for Power11 > ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine > ppc/pnv: Update skiboot to support Power11 > > docs/system/ppc/powernv.rst | 9 +- > hw/ppc/pnv.c | 177 ++++++++++++++++++++++++- > hw/ppc/pnv_chiptod.c | 37 ++++++ > hw/ppc/pnv_core.c | 11 ++ > hw/ppc/pnv_homer.c | 8 ++ > hw/ppc/pnv_lpc.c | 14 ++ > hw/ppc/pnv_occ.c | 14 ++ > hw/ppc/pnv_psi.c | 24 ++++ > hw/ppc/pnv_sbe.c | 15 +++ > include/hw/ppc/pnv.h | 5 + > include/hw/ppc/pnv_chip.h | 7 + > include/hw/ppc/pnv_chiptod.h | 2 + > include/hw/ppc/pnv_core.h | 1 + > include/hw/ppc/pnv_homer.h | 3 + > include/hw/ppc/pnv_lpc.h | 4 + > include/hw/ppc/pnv_occ.h | 2 + > include/hw/ppc/pnv_psi.h | 2 +- > include/hw/ppc/pnv_sbe.h | 2 + > pc-bios/skiboot.lid | Bin 2527328 -> 2527424 bytes > 19 files changed, 321 insertions(+), 10 deletions(-) >
Hi Cedric, On 24/03/25 13:11, Cédric Le Goater wrote: > Hello Aditya, > > On 3/8/25 21:51, Aditya Gupta wrote: >> Overview >> ============ >> >> Add support for Power11 powernv machine type, to emulate PowerNV VMs >> running on Power11. > > Could you please consider deprecating the POWER8NVL and POWER8E CPUs > and associated chips and machines ? I think keeping POWER8 is fine > since it has different HW implementation from the following generations. > However, the POWER8NVL and POWER8E variants don't add much to QEMU. > They were practical at one point for bringup (2014). They are not > anymore. > > This will remove some lpc peculiarities. I don't know how we 'mark' something deprecated in qemu. Checked the git history. By deprecating, should I just mention it in deprecated section in documentation like done for PSeries in commit 0cac0f1b ? Or directly remove it ? Thanks, - Aditya G > > > Thanks, > > C. >
Hello, >> Could you please consider deprecating the POWER8NVL and POWER8E CPUs >> and associated chips and machines ? I think keeping POWER8 is fine >> since it has different HW implementation from the following generations. >> However, the POWER8NVL and POWER8E variants don't add much to QEMU. >> They were practical at one point for bringup (2014). They are not >> anymore. >> >> This will remove some lpc peculiarities. > > > I don't know how we 'mark' something deprecated in qemu. Checked the git history. > > By deprecating, should I just mention it in deprecated section in documentation like done for PSeries in commit 0cac0f1b ? commit 1392617d3576 is an example. versioned machine types are special now and will be automatically deprecated and removed. powernv machines are not though. > Or directly remove it ?. nope. See : https://www.qemu.org/docs/master/about/deprecated.html. Thanks, C.
>>> Could you please consider deprecating the POWER8NVL and POWER8E CPUs >>> and associated chips and machines ? I think keeping POWER8 is fine >>> since it has different HW implementation from the following >>> generations. >>> However, the POWER8NVL and POWER8E variants don't add much to QEMU. >>> They were practical at one point for bringup (2014). They are not >>> anymore. >>> >>> This will remove some lpc peculiarities. >> >> >> I don't know how we 'mark' something deprecated in qemu. Checked the >> git history. >> >> By deprecating, should I just mention it in deprecated section in >> documentation like done for PSeries in commit 0cac0f1b ? > > commit 1392617d3576 is an example. > > versioned machine types are special now and will be automatically > deprecated and removed. powernv machines are not though. > >> Or directly remove it ?. > > nope. See : > > https://www.qemu.org/docs/master/about/deprecated.html. > > Thanks Cédric ! I see we have .deprecation_reason and fields like that, will use those to mark the chips and machine deprecated. - Aditya G > Thanks, > > C. > >
On 3/25/25 18:11, Aditya Gupta wrote: >>>> Could you please consider deprecating the POWER8NVL and POWER8E CPUs >>>> and associated chips and machines ? I think keeping POWER8 is fine >>>> since it has different HW implementation from the following generations. >>>> However, the POWER8NVL and POWER8E variants don't add much to QEMU. >>>> They were practical at one point for bringup (2014). They are not >>>> anymore. >>>> >>>> This will remove some lpc peculiarities. >>> >>> >>> I don't know how we 'mark' something deprecated in qemu. Checked the git history. >>> >>> By deprecating, should I just mention it in deprecated section in documentation like done for PSeries in commit 0cac0f1b ? >> >> commit 1392617d3576 is an example. >> >> versioned machine types are special now and will be automatically >> deprecated and removed. powernv machines are not though. >> >>> Or directly remove it ?. >> >> nope. See : >> >> https://www.qemu.org/docs/master/about/deprecated.html. >> >> > Thanks Cédric ! > > I see we have .deprecation_reason and fields like that, will use those to mark the chips and machine deprecated. yes. That's unrelated to this series though. Thanks, C.
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