accel/tcg/tb-internal.h | 27 +++++++++++++++++++++++++++ include/exec/cpu-defs.h | 26 -------------------------- 2 files changed, 27 insertions(+), 26 deletions(-)
CPU_TLB_DYN_*_BITS definitions are only used by accel/tcg/cputlb.c
and accel/tcg/translate-all.c. Move them to accel/tcg/tb-internal.h.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
accel/tcg/tb-internal.h | 27 +++++++++++++++++++++++++++
include/exec/cpu-defs.h | 26 --------------------------
2 files changed, 27 insertions(+), 26 deletions(-)
diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h
index 90be61f296a..abd423fcf58 100644
--- a/accel/tcg/tb-internal.h
+++ b/accel/tcg/tb-internal.h
@@ -13,6 +13,33 @@
#include "exec/exec-all.h"
#include "exec/translation-block.h"
+#ifdef CONFIG_SOFTMMU
+
+#define CPU_TLB_DYN_MIN_BITS 6
+#define CPU_TLB_DYN_DEFAULT_BITS 8
+
+# if HOST_LONG_BITS == 32
+/* Make sure we do not require a double-word shift for the TLB load */
+# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS)
+# else /* HOST_LONG_BITS == 64 */
+/*
+ * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) ==
+ * 2**34 == 16G of address space. This is roughly what one would expect a
+ * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel
+ * Skylake's Level-2 STLB has 16 1G entries.
+ * Also, make sure we do not size the TLB past the guest's address space.
+ */
+# ifdef TARGET_PAGE_BITS_VARY
+# define CPU_TLB_DYN_MAX_BITS \
+ MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
+# else
+# define CPU_TLB_DYN_MAX_BITS \
+ MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
+# endif
+# endif
+
+#endif /* CONFIG_SOFTMMU */
+
#ifdef CONFIG_USER_ONLY
#include "user/page-protection.h"
/*
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index ae18398fa99..9f955f53fde 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -46,30 +46,4 @@
#include "exec/target_long.h"
-#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
-#define CPU_TLB_DYN_MIN_BITS 6
-#define CPU_TLB_DYN_DEFAULT_BITS 8
-
-# if HOST_LONG_BITS == 32
-/* Make sure we do not require a double-word shift for the TLB load */
-# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS)
-# else /* HOST_LONG_BITS == 64 */
-/*
- * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) ==
- * 2**34 == 16G of address space. This is roughly what one would expect a
- * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel
- * Skylake's Level-2 STLB has 16 1G entries.
- * Also, make sure we do not size the TLB past the guest's address space.
- */
-# ifdef TARGET_PAGE_BITS_VARY
-# define CPU_TLB_DYN_MAX_BITS \
- MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
-# else
-# define CPU_TLB_DYN_MAX_BITS \
- MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
-# endif
-# endif
-
-#endif /* CONFIG_SOFTMMU && CONFIG_TCG */
-
#endif
--
2.47.1
On 3/5/25 11:18, Philippe Mathieu-Daudé wrote: > CPU_TLB_DYN_*_BITS definitions are only used by accel/tcg/cputlb.c > and accel/tcg/translate-all.c. Move them to accel/tcg/tb-internal.h. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > accel/tcg/tb-internal.h | 27 +++++++++++++++++++++++++++ > include/exec/cpu-defs.h | 26 -------------------------- > 2 files changed, 27 insertions(+), 26 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ > > diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h > index 90be61f296a..abd423fcf58 100644 > --- a/accel/tcg/tb-internal.h > +++ b/accel/tcg/tb-internal.h > @@ -13,6 +13,33 @@ > #include "exec/exec-all.h" > #include "exec/translation-block.h" > > +#ifdef CONFIG_SOFTMMU > + > +#define CPU_TLB_DYN_MIN_BITS 6 > +#define CPU_TLB_DYN_DEFAULT_BITS 8 > + > +# if HOST_LONG_BITS == 32 > +/* Make sure we do not require a double-word shift for the TLB load */ > +# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) > +# else /* HOST_LONG_BITS == 64 */ > +/* > + * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == > + * 2**34 == 16G of address space. This is roughly what one would expect a > + * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel > + * Skylake's Level-2 STLB has 16 1G entries. > + * Also, make sure we do not size the TLB past the guest's address space. > + */ > +# ifdef TARGET_PAGE_BITS_VARY > +# define CPU_TLB_DYN_MAX_BITS \ > + MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) > +# else > +# define CPU_TLB_DYN_MAX_BITS \ > + MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) > +# endif > +# endif > + > +#endif /* CONFIG_SOFTMMU */ > + > #ifdef CONFIG_USER_ONLY > #include "user/page-protection.h" > /* > diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h > index ae18398fa99..9f955f53fde 100644 > --- a/include/exec/cpu-defs.h > +++ b/include/exec/cpu-defs.h > @@ -46,30 +46,4 @@ > > #include "exec/target_long.h" > > -#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG) > -#define CPU_TLB_DYN_MIN_BITS 6 > -#define CPU_TLB_DYN_DEFAULT_BITS 8 > - > -# if HOST_LONG_BITS == 32 > -/* Make sure we do not require a double-word shift for the TLB load */ > -# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) > -# else /* HOST_LONG_BITS == 64 */ > -/* > - * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == > - * 2**34 == 16G of address space. This is roughly what one would expect a > - * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel > - * Skylake's Level-2 STLB has 16 1G entries. > - * Also, make sure we do not size the TLB past the guest's address space. > - */ > -# ifdef TARGET_PAGE_BITS_VARY > -# define CPU_TLB_DYN_MAX_BITS \ > - MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) > -# else > -# define CPU_TLB_DYN_MAX_BITS \ > - MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) > -# endif > -# endif > - > -#endif /* CONFIG_SOFTMMU && CONFIG_TCG */ > - > #endif
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