From: Eric Auger <eric.auger@redhat.com>
This new header contains macros that define aarch64 registers.
In a subsequent patch, this will be replaced by a more exhaustive
version that will be generated from linux arch/arm64/tools/sysreg
file. Those macros are sufficient to migrate the storage of those
ID regs from named fields in isar struct to an array cell.
[CH: reworked to use different structures]
[CH: moved accessors from the patches first using them to here,
dropped interaction with writable registers, which will happen
later]
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-sysregs.h | 131 +++++++++++++++++++++++++++++++++++++++
target/arm/cpu.h | 49 +++++++++++++++
2 files changed, 180 insertions(+)
create mode 100644 target/arm/cpu-sysregs.h
diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
new file mode 100644
index 000000000000..de09ebae91a5
--- /dev/null
+++ b/target/arm/cpu-sysregs.h
@@ -0,0 +1,131 @@
+#ifndef ARM_CPU_SYSREGS_H
+#define ARM_CPU_SYSREGS_H
+
+/*
+ * Following is similar to the coprocessor regs encodings, but with an argument
+ * ordering that matches the ARM ARM. We also reuse the various CP_REG_ defines
+ * that actually are the same as the equivalent KVM_REG_ values.
+ */
+#define ENCODE_ID_REG(op0, op1, crn, crm, op2) \
+ (((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
+ ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
+ ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
+ ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
+ ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
+
+typedef enum ARMIDRegisterIdx {
+ ID_AA64PFR0_EL1_IDX,
+ ID_AA64PFR1_EL1_IDX,
+ ID_AA64SMFR0_EL1_IDX,
+ ID_AA64DFR0_EL1_IDX,
+ ID_AA64DFR1_EL1_IDX,
+ ID_AA64ISAR0_EL1_IDX,
+ ID_AA64ISAR1_EL1_IDX,
+ ID_AA64ISAR2_EL1_IDX,
+ ID_AA64MMFR0_EL1_IDX,
+ ID_AA64MMFR1_EL1_IDX,
+ ID_AA64MMFR2_EL1_IDX,
+ ID_AA64MMFR3_EL1_IDX,
+ ID_PFR0_EL1_IDX,
+ ID_PFR1_EL1_IDX,
+ ID_DFR0_EL1_IDX,
+ ID_MMFR0_EL1_IDX,
+ ID_MMFR1_EL1_IDX,
+ ID_MMFR2_EL1_IDX,
+ ID_MMFR3_EL1_IDX,
+ ID_ISAR0_EL1_IDX,
+ ID_ISAR1_EL1_IDX,
+ ID_ISAR2_EL1_IDX,
+ ID_ISAR3_EL1_IDX,
+ ID_ISAR4_EL1_IDX,
+ ID_ISAR5_EL1_IDX,
+ ID_MMFR4_EL1_IDX,
+ ID_ISAR6_EL1_IDX,
+ MVFR0_EL1_IDX,
+ MVFR1_EL1_IDX,
+ MVFR2_EL1_IDX,
+ ID_PFR2_EL1_IDX,
+ ID_DFR1_EL1_IDX,
+ ID_MMFR5_EL1_IDX,
+ ID_AA64ZFR0_EL1_IDX,
+ CTR_EL0_IDX,
+ NUM_ID_IDX,
+} ARMIDRegisterIdx;
+
+typedef enum ARMSysRegs {
+ SYS_ID_AA64PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 0),
+ SYS_ID_AA64PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 1),
+ SYS_ID_AA64SMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 5),
+ SYS_ID_AA64DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 0),
+ SYS_ID_AA64DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 1),
+ SYS_ID_AA64ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 0),
+ SYS_ID_AA64ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 1),
+ SYS_ID_AA64ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 2),
+ SYS_ID_AA64MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 0),
+ SYS_ID_AA64MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 1),
+ SYS_ID_AA64MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 2),
+ SYS_ID_AA64MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 3),
+ SYS_ID_PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 0),
+ SYS_ID_PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 1),
+ SYS_ID_DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 2),
+ SYS_ID_MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 4),
+ SYS_ID_MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 5),
+ SYS_ID_MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 6),
+ SYS_ID_MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 7),
+ SYS_ID_ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 0),
+ SYS_ID_ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 1),
+ SYS_ID_ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 2),
+ SYS_ID_ISAR3_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 3),
+ SYS_ID_ISAR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 4),
+ SYS_ID_ISAR5_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 5),
+ SYS_ID_MMFR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 6),
+ SYS_ID_ISAR6_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 7),
+ SYS_MVFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 0),
+ SYS_MVFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 1),
+ SYS_MVFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 2),
+ SYS_ID_PFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 4),
+ SYS_ID_DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 5),
+ SYS_ID_MMFR5_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 6),
+ SYS_ID_AA64ZFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 4),
+ SYS_CTR_EL0 = ENCODE_ID_REG(3, 3, 0, 0, 1),
+} ARMSysRegs;
+
+static const uint32_t id_register_sysreg[NUM_ID_IDX] = {
+ [ID_AA64PFR0_EL1_IDX] = SYS_ID_AA64PFR0_EL1,
+ [ID_AA64PFR1_EL1_IDX] = SYS_ID_AA64PFR1_EL1,
+ [ID_AA64SMFR0_EL1_IDX] = SYS_ID_AA64SMFR0_EL1,
+ [ID_AA64DFR0_EL1_IDX] = SYS_ID_AA64DFR0_EL1,
+ [ID_AA64DFR1_EL1_IDX] = SYS_ID_AA64DFR1_EL1,
+ [ID_AA64ISAR0_EL1_IDX] = SYS_ID_AA64ISAR0_EL1,
+ [ID_AA64ISAR1_EL1_IDX] = SYS_ID_AA64ISAR1_EL1,
+ [ID_AA64ISAR2_EL1_IDX] = SYS_ID_AA64ISAR2_EL1,
+ [ID_AA64MMFR0_EL1_IDX] = SYS_ID_AA64MMFR0_EL1,
+ [ID_AA64MMFR1_EL1_IDX] = SYS_ID_AA64MMFR1_EL1,
+ [ID_AA64MMFR2_EL1_IDX] = SYS_ID_AA64MMFR2_EL1,
+ [ID_AA64MMFR3_EL1_IDX] = SYS_ID_AA64MMFR3_EL1,
+ [ID_PFR0_EL1_IDX] = SYS_ID_PFR0_EL1,
+ [ID_PFR1_EL1_IDX] = SYS_ID_PFR1_EL1,
+ [ID_DFR0_EL1_IDX] = SYS_ID_DFR0_EL1,
+ [ID_MMFR0_EL1_IDX] = SYS_ID_MMFR0_EL1,
+ [ID_MMFR1_EL1_IDX] = SYS_ID_MMFR1_EL1,
+ [ID_MMFR2_EL1_IDX] = SYS_ID_MMFR2_EL1,
+ [ID_MMFR3_EL1_IDX] = SYS_ID_MMFR3_EL1,
+ [ID_ISAR0_EL1_IDX] = SYS_ID_ISAR0_EL1,
+ [ID_ISAR1_EL1_IDX] = SYS_ID_ISAR1_EL1,
+ [ID_ISAR2_EL1_IDX] = SYS_ID_ISAR2_EL1,
+ [ID_ISAR3_EL1_IDX] = SYS_ID_ISAR3_EL1,
+ [ID_ISAR4_EL1_IDX] = SYS_ID_ISAR4_EL1,
+ [ID_ISAR5_EL1_IDX] = SYS_ID_ISAR5_EL1,
+ [ID_MMFR4_EL1_IDX] = SYS_ID_MMFR4_EL1,
+ [ID_ISAR6_EL1_IDX] = SYS_ID_ISAR6_EL1,
+ [MVFR0_EL1_IDX] = SYS_MVFR0_EL1,
+ [MVFR1_EL1_IDX] = SYS_MVFR1_EL1,
+ [MVFR2_EL1_IDX] = SYS_MVFR2_EL1,
+ [ID_PFR2_EL1_IDX] = SYS_ID_PFR2_EL1,
+ [ID_DFR1_EL1_IDX] = SYS_ID_DFR1_EL1,
+ [ID_MMFR5_EL1_IDX] = SYS_ID_MMFR5_EL1,
+ [ID_AA64ZFR0_EL1_IDX] = SYS_ID_AA64ZFR0_EL1,
+ [CTR_EL0_IDX] = SYS_CTR_EL0,
+};
+
+#endif /* ARM_CPU_SYSREGS_H */
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 215845c7e256..60335f8893fa 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -30,6 +30,7 @@
#include "qapi/qapi-types-common.h"
#include "target/arm/multiprocessing.h"
#include "target/arm/gtimer.h"
+#include "target/arm/cpu-sysregs.h"
#ifdef TARGET_AARCH64
#define KVM_HAVE_MCE_INJECTION 1
@@ -855,6 +856,53 @@ typedef struct {
uint32_t map, init, supported;
} ARMVQMap;
+/* REG is ID_XXX */
+#define FIELD_DP64_IDREG(ISAR, REG, FIELD, VALUE) \
+ ({ \
+ ARMISARegisters *i_ = (ISAR); \
+ uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \
+ regval = FIELD_DP64(regval, REG, FIELD, VALUE); \
+ i_->idregs[REG ## _EL1_IDX] = regval; \
+ })
+
+#define FIELD_DP32_IDREG(ISAR, REG, FIELD, VALUE) \
+ ({ \
+ ARMISARegisters *i_ = (ISAR); \
+ uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \
+ regval = FIELD_DP32(regval, REG, FIELD, VALUE); \
+ i_->idregs[REG ## _EL1_IDX] = regval; \
+ })
+
+#define FIELD_EX64_IDREG(ISAR, REG, FIELD) \
+ ({ \
+ const ARMISARegisters *i_ = (ISAR); \
+ FIELD_EX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
+ })
+
+#define FIELD_EX32_IDREG(ISAR, REG, FIELD) \
+ ({ \
+ const ARMISARegisters *i_ = (ISAR); \
+ FIELD_EX32(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
+ })
+
+#define FIELD_SEX64_IDREG(ISAR, REG, FIELD) \
+ ({ \
+ const ARMISARegisters *i_ = (ISAR); \
+ FIELD_SEX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
+ })
+
+#define SET_IDREG(ISAR, REG, VALUE) \
+ ({ \
+ ARMISARegisters *i_ = (ISAR); \
+ i_->idregs[REG ## _EL1_IDX] = VALUE; \
+ })
+
+#define GET_IDREG(ISAR, REG) \
+ ({ \
+ const ARMISARegisters *i_ = (ISAR); \
+ i_->idregs[REG ## _EL1_IDX]; \
+ })
+
/**
* ARMCPU:
* @env: #CPUARMState
@@ -1063,6 +1111,7 @@ struct ArchCPU {
uint64_t id_aa64zfr0;
uint64_t id_aa64smfr0;
uint64_t reset_pmcr_el0;
+ uint64_t idregs[NUM_ID_IDX];
} isar;
uint64_t midr;
uint32_t revidr;
--
2.48.1On 3/5/25 08:38, Cornelia Huck wrote:
> +++ b/target/arm/cpu-sysregs.h
> @@ -0,0 +1,131 @@
> +#ifndef ARM_CPU_SYSREGS_H
> +#define ARM_CPU_SYSREGS_H
> +
> +/*
> + * Following is similar to the coprocessor regs encodings, but with an argument
> + * ordering that matches the ARM ARM. We also reuse the various CP_REG_ defines
> + * that actually are the same as the equivalent KVM_REG_ values.
> + */
> +#define ENCODE_ID_REG(op0, op1, crn, crm, op2) \
> + (((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
> + ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
> + ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
> + ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
> + ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
> +
> +typedef enum ARMIDRegisterIdx {
> + ID_AA64PFR0_EL1_IDX,
> + ID_AA64PFR1_EL1_IDX,
> + ID_AA64SMFR0_EL1_IDX,
> + ID_AA64DFR0_EL1_IDX,
> + ID_AA64DFR1_EL1_IDX,
> + ID_AA64ISAR0_EL1_IDX,
> + ID_AA64ISAR1_EL1_IDX,
> + ID_AA64ISAR2_EL1_IDX,
> + ID_AA64MMFR0_EL1_IDX,
> + ID_AA64MMFR1_EL1_IDX,
> + ID_AA64MMFR2_EL1_IDX,
> + ID_AA64MMFR3_EL1_IDX,
> + ID_PFR0_EL1_IDX,
> + ID_PFR1_EL1_IDX,
> + ID_DFR0_EL1_IDX,
> + ID_MMFR0_EL1_IDX,
> + ID_MMFR1_EL1_IDX,
> + ID_MMFR2_EL1_IDX,
> + ID_MMFR3_EL1_IDX,
> + ID_ISAR0_EL1_IDX,
> + ID_ISAR1_EL1_IDX,
> + ID_ISAR2_EL1_IDX,
> + ID_ISAR3_EL1_IDX,
> + ID_ISAR4_EL1_IDX,
> + ID_ISAR5_EL1_IDX,
> + ID_MMFR4_EL1_IDX,
> + ID_ISAR6_EL1_IDX,
> + MVFR0_EL1_IDX,
> + MVFR1_EL1_IDX,
> + MVFR2_EL1_IDX,
> + ID_PFR2_EL1_IDX,
> + ID_DFR1_EL1_IDX,
> + ID_MMFR5_EL1_IDX,
> + ID_AA64ZFR0_EL1_IDX,
> + CTR_EL0_IDX,
> + NUM_ID_IDX,
> +} ARMIDRegisterIdx;
> +
> +typedef enum ARMSysRegs {
> + SYS_ID_AA64PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 0),
> + SYS_ID_AA64PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 1),
> + SYS_ID_AA64SMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 5),
> + SYS_ID_AA64DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 0),
> + SYS_ID_AA64DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 1),
> + SYS_ID_AA64ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 0),
> + SYS_ID_AA64ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 1),
> + SYS_ID_AA64ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 2),
> + SYS_ID_AA64MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 0),
> + SYS_ID_AA64MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 1),
> + SYS_ID_AA64MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 2),
> + SYS_ID_AA64MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 3),
> + SYS_ID_PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 0),
> + SYS_ID_PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 1),
> + SYS_ID_DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 2),
> + SYS_ID_MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 4),
> + SYS_ID_MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 5),
> + SYS_ID_MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 6),
> + SYS_ID_MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 7),
> + SYS_ID_ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 0),
> + SYS_ID_ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 1),
> + SYS_ID_ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 2),
> + SYS_ID_ISAR3_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 3),
> + SYS_ID_ISAR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 4),
> + SYS_ID_ISAR5_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 5),
> + SYS_ID_MMFR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 6),
> + SYS_ID_ISAR6_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 7),
> + SYS_MVFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 0),
> + SYS_MVFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 1),
> + SYS_MVFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 2),
> + SYS_ID_PFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 4),
> + SYS_ID_DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 5),
> + SYS_ID_MMFR5_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 6),
> + SYS_ID_AA64ZFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 4),
> + SYS_CTR_EL0 = ENCODE_ID_REG(3, 3, 0, 0, 1),
> +} ARMSysRegs;
> +
> +static const uint32_t id_register_sysreg[NUM_ID_IDX] = {
> + [ID_AA64PFR0_EL1_IDX] = SYS_ID_AA64PFR0_EL1,
> + [ID_AA64PFR1_EL1_IDX] = SYS_ID_AA64PFR1_EL1,
> + [ID_AA64SMFR0_EL1_IDX] = SYS_ID_AA64SMFR0_EL1,
> + [ID_AA64DFR0_EL1_IDX] = SYS_ID_AA64DFR0_EL1,
> + [ID_AA64DFR1_EL1_IDX] = SYS_ID_AA64DFR1_EL1,
> + [ID_AA64ISAR0_EL1_IDX] = SYS_ID_AA64ISAR0_EL1,
> + [ID_AA64ISAR1_EL1_IDX] = SYS_ID_AA64ISAR1_EL1,
> + [ID_AA64ISAR2_EL1_IDX] = SYS_ID_AA64ISAR2_EL1,
> + [ID_AA64MMFR0_EL1_IDX] = SYS_ID_AA64MMFR0_EL1,
> + [ID_AA64MMFR1_EL1_IDX] = SYS_ID_AA64MMFR1_EL1,
> + [ID_AA64MMFR2_EL1_IDX] = SYS_ID_AA64MMFR2_EL1,
> + [ID_AA64MMFR3_EL1_IDX] = SYS_ID_AA64MMFR3_EL1,
> + [ID_PFR0_EL1_IDX] = SYS_ID_PFR0_EL1,
> + [ID_PFR1_EL1_IDX] = SYS_ID_PFR1_EL1,
> + [ID_DFR0_EL1_IDX] = SYS_ID_DFR0_EL1,
> + [ID_MMFR0_EL1_IDX] = SYS_ID_MMFR0_EL1,
> + [ID_MMFR1_EL1_IDX] = SYS_ID_MMFR1_EL1,
> + [ID_MMFR2_EL1_IDX] = SYS_ID_MMFR2_EL1,
> + [ID_MMFR3_EL1_IDX] = SYS_ID_MMFR3_EL1,
> + [ID_ISAR0_EL1_IDX] = SYS_ID_ISAR0_EL1,
> + [ID_ISAR1_EL1_IDX] = SYS_ID_ISAR1_EL1,
> + [ID_ISAR2_EL1_IDX] = SYS_ID_ISAR2_EL1,
> + [ID_ISAR3_EL1_IDX] = SYS_ID_ISAR3_EL1,
> + [ID_ISAR4_EL1_IDX] = SYS_ID_ISAR4_EL1,
> + [ID_ISAR5_EL1_IDX] = SYS_ID_ISAR5_EL1,
> + [ID_MMFR4_EL1_IDX] = SYS_ID_MMFR4_EL1,
> + [ID_ISAR6_EL1_IDX] = SYS_ID_ISAR6_EL1,
> + [MVFR0_EL1_IDX] = SYS_MVFR0_EL1,
> + [MVFR1_EL1_IDX] = SYS_MVFR1_EL1,
> + [MVFR2_EL1_IDX] = SYS_MVFR2_EL1,
> + [ID_PFR2_EL1_IDX] = SYS_ID_PFR2_EL1,
> + [ID_DFR1_EL1_IDX] = SYS_ID_DFR1_EL1,
> + [ID_MMFR5_EL1_IDX] = SYS_ID_MMFR5_EL1,
> + [ID_AA64ZFR0_EL1_IDX] = SYS_ID_AA64ZFR0_EL1,
> + [CTR_EL0_IDX] = SYS_CTR_EL0,
> +};
Again, you should NOT place this array in a header,
to be replicated in every single user of the header.
This can be a bit more automated to avoid mistakes.
--- target/arm/cpu-sysregs.h.inc
DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
...
--- target/arm/cpu-sysregs.h
#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) NAME##_IDX,
typedef enum ARMIDRegisterIdx {
#include "cpu-sysregs.h.inc"
} ARMIDRegisterIdx;
#undef DEF
#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \
SYS_##NAME = ENCODE_ID_REG(OP0, OP1, CRN, CRM, OP2),
typedef enum ARMSysRegs {
#include "cpu-sysregs.h.inc"
} ARMSysRegs;
#undef DEF
r~
On Wed, Mar 05 2025, Richard Henderson <richard.henderson@linaro.org> wrote:
> On 3/5/25 08:38, Cornelia Huck wrote:
>> +++ b/target/arm/cpu-sysregs.h
>> @@ -0,0 +1,131 @@
>> +#ifndef ARM_CPU_SYSREGS_H
>> +#define ARM_CPU_SYSREGS_H
>> +
>> +/*
>> + * Following is similar to the coprocessor regs encodings, but with an argument
>> + * ordering that matches the ARM ARM. We also reuse the various CP_REG_ defines
>> + * that actually are the same as the equivalent KVM_REG_ values.
>> + */
>> +#define ENCODE_ID_REG(op0, op1, crn, crm, op2) \
>> + (((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
>> + ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
>> + ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
>> + ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
>> + ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
>> +
>> +typedef enum ARMIDRegisterIdx {
>> + ID_AA64PFR0_EL1_IDX,
>> + ID_AA64PFR1_EL1_IDX,
>> + ID_AA64SMFR0_EL1_IDX,
>> + ID_AA64DFR0_EL1_IDX,
>> + ID_AA64DFR1_EL1_IDX,
>> + ID_AA64ISAR0_EL1_IDX,
>> + ID_AA64ISAR1_EL1_IDX,
>> + ID_AA64ISAR2_EL1_IDX,
>> + ID_AA64MMFR0_EL1_IDX,
>> + ID_AA64MMFR1_EL1_IDX,
>> + ID_AA64MMFR2_EL1_IDX,
>> + ID_AA64MMFR3_EL1_IDX,
>> + ID_PFR0_EL1_IDX,
>> + ID_PFR1_EL1_IDX,
>> + ID_DFR0_EL1_IDX,
>> + ID_MMFR0_EL1_IDX,
>> + ID_MMFR1_EL1_IDX,
>> + ID_MMFR2_EL1_IDX,
>> + ID_MMFR3_EL1_IDX,
>> + ID_ISAR0_EL1_IDX,
>> + ID_ISAR1_EL1_IDX,
>> + ID_ISAR2_EL1_IDX,
>> + ID_ISAR3_EL1_IDX,
>> + ID_ISAR4_EL1_IDX,
>> + ID_ISAR5_EL1_IDX,
>> + ID_MMFR4_EL1_IDX,
>> + ID_ISAR6_EL1_IDX,
>> + MVFR0_EL1_IDX,
>> + MVFR1_EL1_IDX,
>> + MVFR2_EL1_IDX,
>> + ID_PFR2_EL1_IDX,
>> + ID_DFR1_EL1_IDX,
>> + ID_MMFR5_EL1_IDX,
>> + ID_AA64ZFR0_EL1_IDX,
>> + CTR_EL0_IDX,
>> + NUM_ID_IDX,
>> +} ARMIDRegisterIdx;
>> +
>> +typedef enum ARMSysRegs {
>> + SYS_ID_AA64PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 0),
>> + SYS_ID_AA64PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 1),
>> + SYS_ID_AA64SMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 5),
>> + SYS_ID_AA64DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 0),
>> + SYS_ID_AA64DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 1),
>> + SYS_ID_AA64ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 0),
>> + SYS_ID_AA64ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 1),
>> + SYS_ID_AA64ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 2),
>> + SYS_ID_AA64MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 0),
>> + SYS_ID_AA64MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 1),
>> + SYS_ID_AA64MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 2),
>> + SYS_ID_AA64MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 3),
>> + SYS_ID_PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 0),
>> + SYS_ID_PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 1),
>> + SYS_ID_DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 2),
>> + SYS_ID_MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 4),
>> + SYS_ID_MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 5),
>> + SYS_ID_MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 6),
>> + SYS_ID_MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 7),
>> + SYS_ID_ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 0),
>> + SYS_ID_ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 1),
>> + SYS_ID_ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 2),
>> + SYS_ID_ISAR3_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 3),
>> + SYS_ID_ISAR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 4),
>> + SYS_ID_ISAR5_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 5),
>> + SYS_ID_MMFR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 6),
>> + SYS_ID_ISAR6_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 7),
>> + SYS_MVFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 0),
>> + SYS_MVFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 1),
>> + SYS_MVFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 2),
>> + SYS_ID_PFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 4),
>> + SYS_ID_DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 5),
>> + SYS_ID_MMFR5_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 6),
>> + SYS_ID_AA64ZFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 4),
>> + SYS_CTR_EL0 = ENCODE_ID_REG(3, 3, 0, 0, 1),
>> +} ARMSysRegs;
>> +
>> +static const uint32_t id_register_sysreg[NUM_ID_IDX] = {
>> + [ID_AA64PFR0_EL1_IDX] = SYS_ID_AA64PFR0_EL1,
>> + [ID_AA64PFR1_EL1_IDX] = SYS_ID_AA64PFR1_EL1,
>> + [ID_AA64SMFR0_EL1_IDX] = SYS_ID_AA64SMFR0_EL1,
>> + [ID_AA64DFR0_EL1_IDX] = SYS_ID_AA64DFR0_EL1,
>> + [ID_AA64DFR1_EL1_IDX] = SYS_ID_AA64DFR1_EL1,
>> + [ID_AA64ISAR0_EL1_IDX] = SYS_ID_AA64ISAR0_EL1,
>> + [ID_AA64ISAR1_EL1_IDX] = SYS_ID_AA64ISAR1_EL1,
>> + [ID_AA64ISAR2_EL1_IDX] = SYS_ID_AA64ISAR2_EL1,
>> + [ID_AA64MMFR0_EL1_IDX] = SYS_ID_AA64MMFR0_EL1,
>> + [ID_AA64MMFR1_EL1_IDX] = SYS_ID_AA64MMFR1_EL1,
>> + [ID_AA64MMFR2_EL1_IDX] = SYS_ID_AA64MMFR2_EL1,
>> + [ID_AA64MMFR3_EL1_IDX] = SYS_ID_AA64MMFR3_EL1,
>> + [ID_PFR0_EL1_IDX] = SYS_ID_PFR0_EL1,
>> + [ID_PFR1_EL1_IDX] = SYS_ID_PFR1_EL1,
>> + [ID_DFR0_EL1_IDX] = SYS_ID_DFR0_EL1,
>> + [ID_MMFR0_EL1_IDX] = SYS_ID_MMFR0_EL1,
>> + [ID_MMFR1_EL1_IDX] = SYS_ID_MMFR1_EL1,
>> + [ID_MMFR2_EL1_IDX] = SYS_ID_MMFR2_EL1,
>> + [ID_MMFR3_EL1_IDX] = SYS_ID_MMFR3_EL1,
>> + [ID_ISAR0_EL1_IDX] = SYS_ID_ISAR0_EL1,
>> + [ID_ISAR1_EL1_IDX] = SYS_ID_ISAR1_EL1,
>> + [ID_ISAR2_EL1_IDX] = SYS_ID_ISAR2_EL1,
>> + [ID_ISAR3_EL1_IDX] = SYS_ID_ISAR3_EL1,
>> + [ID_ISAR4_EL1_IDX] = SYS_ID_ISAR4_EL1,
>> + [ID_ISAR5_EL1_IDX] = SYS_ID_ISAR5_EL1,
>> + [ID_MMFR4_EL1_IDX] = SYS_ID_MMFR4_EL1,
>> + [ID_ISAR6_EL1_IDX] = SYS_ID_ISAR6_EL1,
>> + [MVFR0_EL1_IDX] = SYS_MVFR0_EL1,
>> + [MVFR1_EL1_IDX] = SYS_MVFR1_EL1,
>> + [MVFR2_EL1_IDX] = SYS_MVFR2_EL1,
>> + [ID_PFR2_EL1_IDX] = SYS_ID_PFR2_EL1,
>> + [ID_DFR1_EL1_IDX] = SYS_ID_DFR1_EL1,
>> + [ID_MMFR5_EL1_IDX] = SYS_ID_MMFR5_EL1,
>> + [ID_AA64ZFR0_EL1_IDX] = SYS_ID_AA64ZFR0_EL1,
>> + [CTR_EL0_IDX] = SYS_CTR_EL0,
>> +};
>
> Again, you should NOT place this array in a header,
> to be replicated in every single user of the header.
Hrm, I thought I had addressed this... but apparently not.
>
>
> This can be a bit more automated to avoid mistakes.
You mean to reduce this to a single invocation of the parsing script?
(The hand-written version is more error prone, I agree.)
>
> --- target/arm/cpu-sysregs.h.inc
>
> DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
> ...
>
> --- target/arm/cpu-sysregs.h
>
> #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) NAME##_IDX,
>
> typedef enum ARMIDRegisterIdx {
> #include "cpu-sysregs.h.inc"
> } ARMIDRegisterIdx;
>
> #undef DEF
> #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \
> SYS_##NAME = ENCODE_ID_REG(OP0, OP1, CRN, CRM, OP2),
>
> typedef enum ARMSysRegs {
> #include "cpu-sysregs.h.inc"
> } ARMSysRegs;
>
> #undef DEF
>
>
> r~
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