target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 5 +++ target/riscv/csr.c | 36 +++++++++++++++++++ target/riscv/debug.c | 76 +++++++++++++++++++++++++++++------------ target/riscv/debug.h | 3 ++ 5 files changed, 100 insertions(+), 21 deletions(-)
Hello, v2: Rebasing the patch series on top of the maintainer's tree. Thank you, Florian Lugou (2): target/riscv: Add scontext CSR handling target/riscv: Support matching scontext in Sdtrig's textra CSRs target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 5 +++ target/riscv/csr.c | 36 +++++++++++++++++++ target/riscv/debug.c | 76 +++++++++++++++++++++++++++++------------ target/riscv/debug.h | 3 ++ 5 files changed, 100 insertions(+), 21 deletions(-) -- 2.43.0