From: Brian Cain <bcain@quicinc.com>

Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/reg_fields_def.h.inc | 11 +++++++++++
 target/hexagon/cpu_helper.c         | 24 ++++++++++++++++++++++++
 2 files changed, 35 insertions(+)

diff --git a/target/hexagon/reg_fields_def.h.inc b/target/hexagon/reg_fields_def.h.inc
index 156a3514e7..50b8c26f8b 100644
--- a/target/hexagon/reg_fields_def.h.inc
+++ b/target/hexagon/reg_fields_def.h.inc
@@ -135,3 +135,14 @@ DEF_REG_FIELD(CCR_GRE, 27, 1)
 DEF_REG_FIELD(CCR_VV1, 29, 1)
 DEF_REG_FIELD(CCR_VV2, 30, 1)
 DEF_REG_FIELD(CCR_VV3, 31, 1)
+
+/* ISDB ST fields */
+DEF_REG_FIELD(ISDBST_WAITRUN, 24, 8)
+DEF_REG_FIELD(ISDBST_ONOFF, 16, 8)
+DEF_REG_FIELD(ISDBST_DEBUGMODE, 8, 8)
+DEF_REG_FIELD(ISDBST_STUFFSTATUS, 5, 1)
+DEF_REG_FIELD(ISDBST_CMDSTATUS, 4, 1)
+DEF_REG_FIELD(ISDBST_PROCMODE, 3, 1)
+DEF_REG_FIELD(ISDBST_MBXINSTATUS, 2, 1)
+DEF_REG_FIELD(ISDBST_MBXOUTSTATUS, 1, 1)
+DEF_REG_FIELD(ISDBST_READY, 0, 1)
diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c
index e64568b9fc..e0dd120cd4 100644
--- a/target/hexagon/cpu_helper.c
+++ b/target/hexagon/cpu_helper.c
@@ -237,6 +237,30 @@ void hexagon_ssr_set_cause(CPUHexagonState *env, uint32_t cause)
 
 int get_exe_mode(CPUHexagonState *env)
 {
+    g_assert(bql_locked());
+
+    target_ulong modectl = arch_get_system_reg(env, HEX_SREG_MODECTL);
+    uint32_t thread_enabled_mask = GET_FIELD(MODECTL_E, modectl);
+    bool E_bit = thread_enabled_mask & (0x1 << env->threadId);
+    uint32_t thread_wait_mask = GET_FIELD(MODECTL_W, modectl);
+    bool W_bit = thread_wait_mask & (0x1 << env->threadId);
+    target_ulong isdbst = arch_get_system_reg(env, HEX_SREG_ISDBST);
+    uint32_t debugmode = GET_FIELD(ISDBST_DEBUGMODE, isdbst);
+    bool D_bit = debugmode & (0x1 << env->threadId);
+
+    /* Figure 4-2 */
+    if (!D_bit && !W_bit && !E_bit) {
+        return HEX_EXE_MODE_OFF;
+    }
+    if (!D_bit && !W_bit && E_bit) {
+        return HEX_EXE_MODE_RUN;
+    }
+    if (!D_bit && W_bit && E_bit) {
+        return HEX_EXE_MODE_WAIT;
+    }
+    if (D_bit && !W_bit && E_bit) {
+        return HEX_EXE_MODE_DEBUG;
+    }
     g_assert_not_reached();
 }
 
-- 
2.34.1

> -----Original Message-----
> From: Brian Cain <brian.cain@oss.qualcomm.com>
> Sent: Friday, February 28, 2025 11:28 PM
> To: qemu-devel@nongnu.org
> Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org;
> philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng;
> quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com;
> alex.bennee@linaro.org; quic_mburton@quicinc.com;
> sidneym@quicinc.com; Brian Cain <bcain@quicinc.com>
> Subject: [PATCH 08/39] target/hexagon: Implement get_exe_mode()
> 
> From: Brian Cain <bcain@quicinc.com>
> 
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>


> diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c
> index e64568b9fc..e0dd120cd4 100644
> --- a/target/hexagon/cpu_helper.c
> +++ b/target/hexagon/cpu_helper.c
> @@ -237,6 +237,30 @@ void hexagon_ssr_set_cause(CPUHexagonState
> *env, uint32_t cause)
> 
>  int get_exe_mode(CPUHexagonState *env)
>  {
> +    g_assert(bql_locked());
> +
> +    target_ulong modectl = arch_get_system_reg(env,
> HEX_SREG_MODECTL);
> +    uint32_t thread_enabled_mask = GET_FIELD(MODECTL_E, modectl);
> +    bool E_bit = thread_enabled_mask & (0x1 << env->threadId);
> +    uint32_t thread_wait_mask = GET_FIELD(MODECTL_W, modectl);
> +    bool W_bit = thread_wait_mask & (0x1 << env->threadId);
> +    target_ulong isdbst = arch_get_system_reg(env, HEX_SREG_ISDBST);
> +    uint32_t debugmode = GET_FIELD(ISDBST_DEBUGMODE, isdbst);
> +    bool D_bit = debugmode & (0x1 << env->threadId);
> +
> +    /* Figure 4-2 */

Figure 4-2 in which document?

Otherwise
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>

On 3/17/2025 1:43 PM, ltaylorsimpson@gmail.com wrote:
>
>> -----Original Message-----
>> From: Brian Cain <brian.cain@oss.qualcomm.com>
>> Sent: Friday, February 28, 2025 11:28 PM
>> To: qemu-devel@nongnu.org
>> Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org;
>> philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng;
>> quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com;
>> alex.bennee@linaro.org; quic_mburton@quicinc.com;
>> sidneym@quicinc.com; Brian Cain <bcain@quicinc.com>
>> Subject: [PATCH 08/39] target/hexagon: Implement get_exe_mode()
>>
>> From: Brian Cain <bcain@quicinc.com>
>>
>> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
>
>> diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c
>> index e64568b9fc..e0dd120cd4 100644
>> --- a/target/hexagon/cpu_helper.c
>> +++ b/target/hexagon/cpu_helper.c
>> @@ -237,6 +237,30 @@ void hexagon_ssr_set_cause(CPUHexagonState
>> *env, uint32_t cause)
>>
>>   int get_exe_mode(CPUHexagonState *env)
>>   {
>> +    g_assert(bql_locked());
>> +
>> +    target_ulong modectl = arch_get_system_reg(env,
>> HEX_SREG_MODECTL);
>> +    uint32_t thread_enabled_mask = GET_FIELD(MODECTL_E, modectl);
>> +    bool E_bit = thread_enabled_mask & (0x1 << env->threadId);
>> +    uint32_t thread_wait_mask = GET_FIELD(MODECTL_W, modectl);
>> +    bool W_bit = thread_wait_mask & (0x1 << env->threadId);
>> +    target_ulong isdbst = arch_get_system_reg(env, HEX_SREG_ISDBST);
>> +    uint32_t debugmode = GET_FIELD(ISDBST_DEBUGMODE, isdbst);
>> +    bool D_bit = debugmode & (0x1 << env->threadId);
>> +
>> +    /* Figure 4-2 */
> Figure 4-2 in which document?


I don't think that document with this figure is published.


I'll just remove the reference instead.

>
> Otherwise
> Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
>
>