From: Brian Cain <bcain@quicinc.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
target/hexagon/gen_analyze_funcs.py | 21 +++-
target/hexagon/hex_common.py | 163 ++++++++++++++++++++++++++++
2 files changed, 181 insertions(+), 3 deletions(-)
diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analyze_funcs.py
index 3ac7cc2cfe..dfdf5f3b87 100755
--- a/target/hexagon/gen_analyze_funcs.py
+++ b/target/hexagon/gen_analyze_funcs.py
@@ -22,6 +22,8 @@
import string
import hex_common
+def has_analyze_func(reg, mode):
+ return callable(getattr(reg, f"analyze_{mode}", None))
##
## Generate the code to analyze the instruction
@@ -42,6 +44,14 @@ def gen_analyze_func(f, tag, regs, imms):
f.write(f"static void analyze_{tag}(DisasContext *ctx)\n")
f.write("{\n")
+ if hex_common.tag_ignore(tag):
+ f.write("}\n\n")
+ return
+
+ if ("A_PRIV" in hex_common.attribdict[tag] or
+ "A_GUEST" in hex_common.attribdict[tag]):
+ f.write("#ifndef CONFIG_USER_ONLY\n")
+
f.write(" Insn *insn G_GNUC_UNUSED = ctx->insn;\n")
if (hex_common.is_hvx_insn(tag)):
if hex_common.has_hvx_helper(tag):
@@ -58,22 +68,27 @@ def gen_analyze_func(f, tag, regs, imms):
for regno, register in enumerate(regs):
reg_type, reg_id = register
reg = hex_common.get_register(tag, reg_type, reg_id)
- reg.decl_reg_num(f, regno)
+ if has_analyze_func(reg, "read") or has_analyze_func(reg, "write"):
+ reg.decl_reg_num(f, regno)
## Analyze the register reads
for regno, register in enumerate(regs):
reg_type, reg_id = register
reg = hex_common.get_register(tag, reg_type, reg_id)
- if reg.is_read():
+ if reg.is_read() and has_analyze_func(reg, "read"):
reg.analyze_read(f, regno)
## Analyze the register writes
for regno, register in enumerate(regs):
reg_type, reg_id = register
reg = hex_common.get_register(tag, reg_type, reg_id)
- if reg.is_written():
+ if reg.is_written() and has_analyze_func(reg, "write"):
reg.analyze_write(f, tag, regno)
+ if ("A_PRIV" in hex_common.attribdict[tag] or
+ "A_GUEST" in hex_common.attribdict[tag]):
+ f.write("#endif /* !CONFIG_USER_ONLY */\n")
+
f.write("}\n\n")
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 758e5fd12d..db50defeb6 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -33,6 +33,41 @@
overrides = {} # tags with helper overrides
idef_parser_enabled = {} # tags enabled for idef-parser
+
+def is_sysemu_tag(tag):
+ return "A_PRIV" in attribdict[tag] or "A_GUEST" in attribdict[tag]
+
+
+def tag_ignore(tag):
+ tag_skips = (
+ "Y6_diag",
+ "Y6_diag0",
+ "Y6_diag1",
+ )
+ attr_skips = (
+ "A_FAKEINSN",
+ "A_MAPPING",
+ )
+ return tag in tag_skips or \
+ any(attr in attribdict[tag] for attr in attr_skips)
+
+
+def get_sys_tags():
+ return sorted(
+ tag for tag in frozenset(tags) if is_sysemu_tag(tag)
+ )
+
+
+def get_user_tags():
+ return sorted(
+ tag for tag in frozenset(tags) if not is_sysemu_tag(tag)
+ )
+
+
+def get_all_tags():
+ return get_user_tags() + get_sys_tags()
+
+
# We should do this as a hash for performance,
# but to keep order let's keep it as a list.
def uniquify(seq):
@@ -366,12 +401,16 @@ def helper_proto_type(self):
return "s32"
def helper_arg_type(self):
return "int32_t"
+ def is_pair(self):
+ return False
class Pair(Scalar):
def helper_proto_type(self):
return "s64"
def helper_arg_type(self):
return "int64_t"
+ def is_pair(self):
+ return True
class Hvx:
def is_scalar_reg(self):
@@ -1009,6 +1048,120 @@ def analyze_write(self, f, tag, regno):
ctx_log_qreg_write(ctx, {self.reg_num}, insn_has_hvx_helper);
"""))
+class GuestRegister(Register):
+ def gen_check_impl(self, f, regno):
+ if self.is_written():
+ f.write(code_fmt(f"""\
+ if (!greg_writable(insn->regno[{regno}],
+ {str(self.is_pair()).lower()})) {{
+ return;
+ }}
+ """))
+ else:
+ f.write(code_fmt(f"""\
+check_greg_impl(insn->regno[{regno}], {str(self.is_pair()).lower()});
+ """))
+
+class GuestDest(GuestRegister, Single, Dest):
+ def decl_tcg(self, f, tag, regno):
+ self.decl_reg_num(f, regno)
+ self.gen_check_impl(f, regno)
+ f.write(code_fmt(f"""\
+ TCGv {self.reg_tcg()} = tcg_temp_new();
+ gen_read_greg({self.reg_tcg()}, {self.reg_num});
+ """))
+ def log_write(self, f, tag):
+ f.write(code_fmt(f"""\
+ gen_log_greg_write(ctx, {self.reg_num}, {self.reg_tcg()});
+ """))
+ def analyze_write(self, f, tag, regno):
+ f.write(code_fmt(f"""\
+ ctx_log_greg_write(ctx, {self.reg_num});
+ """))
+
+class GuestSource(GuestRegister, Single, OldSource):
+ def decl_tcg(self, f, tag, regno):
+ self.decl_reg_num(f, regno);
+ self.gen_check_impl(f, regno)
+ f.write(code_fmt(f"""\
+ TCGv {self.reg_tcg()} = tcg_temp_new();
+ gen_read_greg({self.reg_tcg()}, {self.reg_num});
+ """))
+
+class GuestPairDest(GuestRegister, Pair, Dest):
+ def decl_tcg(self, f, tag, regno):
+ self.decl_reg_num(f, regno)
+ self.gen_check_impl(f, regno)
+ f.write(code_fmt(f"""\
+ TCGv_i64 {self.reg_tcg()} = tcg_temp_new_i64();
+ gen_read_greg_pair({self.reg_tcg()}, {self.reg_num});
+ """))
+ def log_write(self, f, tag):
+ f.write(code_fmt(f"""\
+ gen_log_greg_write_pair(ctx, {self.reg_num}, {self.reg_tcg()});
+ """))
+ def analyze_write(self, f, tag, regno):
+ f.write(code_fmt(f"""\
+ ctx_log_greg_write_pair(ctx, {self.reg_num});
+ """))
+
+class GuestPairSource(GuestRegister, Pair, OldSource):
+ def decl_tcg(self, f, tag, regno):
+ self.decl_reg_num(f, regno)
+ self.gen_check_impl(f, regno)
+ f.write(code_fmt(f"""\
+ TCGv_i64 {self.reg_tcg()} = tcg_temp_new_i64();
+ gen_read_greg_pair({self.reg_tcg()}, {self.reg_num});
+ """))
+
+class SystemDest(Register, Single, Dest):
+ def decl_tcg(self, f, tag, regno):
+ self.decl_reg_num(f, regno)
+ f.write(code_fmt(f"""\
+ TCGv {self.reg_tcg()} = tcg_temp_new();
+ gen_read_sreg({self.reg_tcg()}, {self.reg_num});
+ """))
+ def log_write(self, f, tag):
+ f.write(code_fmt(f"""\
+ gen_log_sreg_write(ctx, {self.reg_num}, {self.reg_tcg()});
+ """))
+ def analyze_write(self, f, tag, regno):
+ f.write(code_fmt(f"""\
+ ctx_log_sreg_write(ctx, {self.reg_num});
+ """))
+
+class SystemSource(Register, Single, OldSource):
+ def decl_tcg(self, f, tag, regno):
+ self.decl_reg_num(f, regno);
+ f.write(code_fmt(f"""\
+ TCGv {self.reg_tcg()} = tcg_temp_new();
+ gen_read_sreg({self.reg_tcg()}, {self.reg_num});
+ """))
+
+class SystemPairDest(Register, Pair, Dest):
+ def decl_tcg(self, f, tag, regno):
+ self.decl_reg_num(f, regno)
+ f.write(code_fmt(f"""\
+ TCGv_i64 {self.reg_tcg()} = tcg_temp_new_i64();
+ gen_read_sreg_pair({self.reg_tcg()}, {self.reg_num});
+ """))
+ def log_write(self, f, tag):
+ f.write(code_fmt(f"""\
+ gen_log_sreg_write_pair(ctx, {self.reg_num}, {self.reg_tcg()});
+ """))
+ def analyze_write(self, f, tag, regno):
+ f.write(code_fmt(f"""\
+ ctx_log_sreg_write_pair(ctx, {self.reg_num});
+ """))
+
+class SystemPairSource(Register, Pair, OldSource):
+ def decl_tcg(self, f, tag, regno):
+ self.decl_reg_num(f, regno)
+ f.write(code_fmt(f"""\
+ TCGv_i64 {self.reg_tcg()} = tcg_temp_new_i64();
+ gen_read_sreg_pair({self.reg_tcg()}, {self.reg_num});
+ """))
+
def init_registers():
regs = {
GprDest("R", "d"),
@@ -1055,6 +1208,16 @@ def init_registers():
QRegSource("Q", "u"),
QRegSource("Q", "v"),
QRegReadWrite("Q", "x"),
+
+ # system regs
+ GuestDest("G", "d"),
+ GuestSource("G", "s"),
+ GuestPairDest("G", "dd"),
+ GuestPairSource("G", "ss"),
+ SystemDest("S", "d"),
+ SystemSource("S", "s"),
+ SystemPairDest("S", "dd"),
+ SystemPairSource("S", "ss"),
}
for reg in regs:
registers[f"{reg.regtype}{reg.regid}"] = reg
--
2.34.1
> -----Original Message-----
> From: Brian Cain <brian.cain@oss.qualcomm.com>
> Sent: Friday, February 28, 2025 10:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org;
> philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng;
> quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com;
> alex.bennee@linaro.org; quic_mburton@quicinc.com;
> sidneym@quicinc.com; Brian Cain <bcain@quicinc.com>
> Subject: [PATCH 03/38] target/hexagon: Add System/Guest register
> definitions
>
> From: Brian Cain <bcain@quicinc.com>
>
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> ---
> target/hexagon/gen_analyze_funcs.py | 21 +++-
> target/hexagon/hex_common.py | 163
> ++++++++++++++++++++++++++++
> 2 files changed, 181 insertions(+), 3 deletions(-)
> diff --git a/target/hexagon/hex_common.py
> b/target/hexagon/hex_common.py index 758e5fd12d..db50defeb6 100755
> --- a/target/hexagon/hex_common.py
> +++ b/target/hexagon/hex_common.py
> @@ -33,6 +33,41 @@
> overrides = {} # tags with helper overrides idef_parser_enabled = {} # tags
> enabled for idef-parser
>
> +
> +def is_sysemu_tag(tag):
> + return "A_PRIV" in attribdict[tag] or "A_GUEST" in attribdict[tag]
> +
> +
> +def tag_ignore(tag):
> + tag_skips = (
> + "Y6_diag",
> + "Y6_diag0",
> + "Y6_diag1",
> + )
> + attr_skips = (
> + "A_FAKEINSN",
> + "A_MAPPING",
Add A_CONDMAPPING to this list.
> + )
> + return tag in tag_skips or \
> + any(attr in attribdict[tag] for attr in attr_skips)
On 4/16/2025 12:54 PM, ltaylorsimpson@gmail.com wrote:
>
>> -----Original Message-----
>> From: Brian Cain <brian.cain@oss.qualcomm.com>
>> Sent: Friday, February 28, 2025 10:26 PM
>> To: qemu-devel@nongnu.org
>> Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org;
>> philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng;
>> quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com;
>> alex.bennee@linaro.org; quic_mburton@quicinc.com;
>> sidneym@quicinc.com; Brian Cain <bcain@quicinc.com>
>> Subject: [PATCH 03/38] target/hexagon: Add System/Guest register
>> definitions
>>
>> From: Brian Cain <bcain@quicinc.com>
>>
>> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
>> ---
>> target/hexagon/gen_analyze_funcs.py | 21 +++-
>> target/hexagon/hex_common.py | 163
>> ++++++++++++++++++++++++++++
>> 2 files changed, 181 insertions(+), 3 deletions(-)
>> diff --git a/target/hexagon/hex_common.py
>> b/target/hexagon/hex_common.py index 758e5fd12d..db50defeb6 100755
>> --- a/target/hexagon/hex_common.py
>> +++ b/target/hexagon/hex_common.py
>> @@ -33,6 +33,41 @@
>> overrides = {} # tags with helper overrides idef_parser_enabled = {} # tags
>> enabled for idef-parser
>>
>> +
>> +def is_sysemu_tag(tag):
>> + return "A_PRIV" in attribdict[tag] or "A_GUEST" in attribdict[tag]
>> +
>> +
>> +def tag_ignore(tag):
>> + tag_skips = (
>> + "Y6_diag",
>> + "Y6_diag0",
>> + "Y6_diag1",
>> + )
>> + attr_skips = (
>> + "A_FAKEINSN",
>> + "A_MAPPING",
> Add A_CONDMAPPING to this list.
Will do.
>> + )
>> + return tag in tag_skips or \
>> + any(attr in attribdict[tag] for attr in attr_skips)
>
>
> -----Original Message-----
> From: Brian Cain <brian.cain@oss.qualcomm.com>
> Sent: Wednesday, April 16, 2025 1:43 PM
> To: ltaylorsimpson@gmail.com; qemu-devel@nongnu.org
> Cc: richard.henderson@linaro.org; philmd@linaro.org;
> quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng;
> quic_mliebel@quicinc.com; alex.bennee@linaro.org;
> quic_mburton@quicinc.com; sidneym@quicinc.com; 'Brian Cain'
> <bcain@quicinc.com>
> Subject: Re: [PATCH 03/38] target/hexagon: Add System/Guest register
> definitions
>
>
> On 4/16/2025 12:54 PM, ltaylorsimpson@gmail.com wrote:
> >
> >> -----Original Message-----
> >> From: Brian Cain <brian.cain@oss.qualcomm.com>
> >> Sent: Friday, February 28, 2025 10:26 PM
> >> To: qemu-devel@nongnu.org
> >> Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org;
> >> philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng;
> >> anjo@rev.ng; quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com;
> >> alex.bennee@linaro.org; quic_mburton@quicinc.com;
> >> sidneym@quicinc.com; Brian Cain <bcain@quicinc.com>
> >> Subject: [PATCH 03/38] target/hexagon: Add System/Guest register
> >> definitions
> >>
> >> From: Brian Cain <bcain@quicinc.com>
> >>
> >> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> >> ---
> >> target/hexagon/gen_analyze_funcs.py | 21 +++-
> >> target/hexagon/hex_common.py | 163
> >> ++++++++++++++++++++++++++++
> >> 2 files changed, 181 insertions(+), 3 deletions(-) diff --git
> >> a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
> index
> >> 758e5fd12d..db50defeb6 100755
> >> --- a/target/hexagon/hex_common.py
> >> +++ b/target/hexagon/hex_common.py
> >> @@ -33,6 +33,41 @@
> >> overrides = {} # tags with helper overrides idef_parser_enabled =
> >> {} # tags enabled for idef-parser
> >>
> >> +
> >> +def is_sysemu_tag(tag):
> >> + return "A_PRIV" in attribdict[tag] or "A_GUEST" in
> >> +attribdict[tag]
> >> +
> >> +
> >> +def tag_ignore(tag):
> >> + tag_skips = (
> >> + "Y6_diag",
> >> + "Y6_diag0",
> >> + "Y6_diag1",
> >> + )
> >> + attr_skips = (
> >> + "A_FAKEINSN",
> >> + "A_MAPPING",
> > Add A_CONDMAPPING to this list.
>
>
> Will do.
Great. Also, make sure tag_ignore is used by all the generator scripts. Then, these won't show up any of the generated files (e.g., opcodes_def_generated.h.inc).
On 4/16/2025 5:02 PM, ltaylorsimpson@gmail.com wrote:
>
>> -----Original Message-----
>> From: Brian Cain <brian.cain@oss.qualcomm.com>
>> Sent: Wednesday, April 16, 2025 1:43 PM
>> To: ltaylorsimpson@gmail.com; qemu-devel@nongnu.org
>> Cc: richard.henderson@linaro.org; philmd@linaro.org;
>> quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng;
>> quic_mliebel@quicinc.com; alex.bennee@linaro.org;
>> quic_mburton@quicinc.com; sidneym@quicinc.com; 'Brian Cain'
>> <bcain@quicinc.com>
>> Subject: Re: [PATCH 03/38] target/hexagon: Add System/Guest register
>> definitions
>>
>>
>> On 4/16/2025 12:54 PM, ltaylorsimpson@gmail.com wrote:
>>>> -----Original Message-----
>>>> From: Brian Cain <brian.cain@oss.qualcomm.com>
>>>> Sent: Friday, February 28, 2025 10:26 PM
>>>> To: qemu-devel@nongnu.org
>>>> Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org;
>>>> philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng;
>>>> anjo@rev.ng; quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com;
>>>> alex.bennee@linaro.org; quic_mburton@quicinc.com;
>>>> sidneym@quicinc.com; Brian Cain <bcain@quicinc.com>
>>>> Subject: [PATCH 03/38] target/hexagon: Add System/Guest register
>>>> definitions
>>>>
>>>> From: Brian Cain <bcain@quicinc.com>
>>>>
>>>> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
>>>> ---
>>>> target/hexagon/gen_analyze_funcs.py | 21 +++-
>>>> target/hexagon/hex_common.py | 163
>>>> ++++++++++++++++++++++++++++
>>>> 2 files changed, 181 insertions(+), 3 deletions(-) diff --git
>>>> a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
>> index
>>>> 758e5fd12d..db50defeb6 100755
>>>> --- a/target/hexagon/hex_common.py
>>>> +++ b/target/hexagon/hex_common.py
>>>> @@ -33,6 +33,41 @@
>>>> overrides = {} # tags with helper overrides idef_parser_enabled =
>>>> {} # tags enabled for idef-parser
>>>>
>>>> +
>>>> +def is_sysemu_tag(tag):
>>>> + return "A_PRIV" in attribdict[tag] or "A_GUEST" in
>>>> +attribdict[tag]
>>>> +
>>>> +
>>>> +def tag_ignore(tag):
>>>> + tag_skips = (
>>>> + "Y6_diag",
>>>> + "Y6_diag0",
>>>> + "Y6_diag1",
>>>> + )
>>>> + attr_skips = (
>>>> + "A_FAKEINSN",
>>>> + "A_MAPPING",
>>> Add A_CONDMAPPING to this list.
>>
>> Will do.
> Great. Also, make sure tag_ignore is used by all the generator scripts. Then, these won't show up any of the generated files (e.g., opcodes_def_generated.h.inc).
The above should be addressed in the v2 patch series (arriving at the
list Real Soon Now).
> -----Original Message-----
> From: Brian Cain <brian.cain@oss.qualcomm.com>
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org;
> philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng;
> quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com;
> alex.bennee@linaro.org; quic_mburton@quicinc.com;
> sidneym@quicinc.com; Brian Cain <bcain@quicinc.com>
> Subject: [PATCH 03/38] target/hexagon: Add System/Guest register
> definitions
>
Based on the subject, I was expecting to see the register definitions in CPUHexagonState. A better description would be
target/hexagon: Handle system/guest registers in gen_analyze_funcs.py and hex_common.py
> From: Brian Cain <bcain@quicinc.com>
>
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> ---
> target/hexagon/gen_analyze_funcs.py | 21 +++-
> target/hexagon/hex_common.py | 163
> ++++++++++++++++++++++++++++
> 2 files changed, 181 insertions(+), 3 deletions(-)
>
> diff --git a/target/hexagon/hex_common.py
> b/target/hexagon/hex_common.py index 758e5fd12d..db50defeb6 100755
> --- a/target/hexagon/hex_common.py
> +++ b/target/hexagon/hex_common.py
> @@ -33,6 +33,41 @@
> overrides = {} # tags with helper overrides idef_parser_enabled = {} # tags
> enabled for idef-parser
>
> +class GuestRegister(Register):
> + def gen_check_impl(self, f, regno):
> + if self.is_written():
> + f.write(code_fmt(f"""\
> + if (!greg_writable(insn->regno[{regno}],
> + {str(self.is_pair()).lower()})) {{
> + return;
> + }}
> + """))
> + else:
> + f.write(code_fmt(f"""\
> +check_greg_impl(insn->regno[{regno}], {str(self.is_pair()).lower()});
You can indent this, the code_fmt function will handle it properly in the output. Are you worried about making the line too long for checkpatch?
> + """))
> +
> +class GuestDest(GuestRegister, Single, Dest):
> + def decl_tcg(self, f, tag, regno):
> + self.decl_reg_num(f, regno)
> + self.gen_check_impl(f, regno)
> + f.write(code_fmt(f"""\
> + TCGv {self.reg_tcg()} = tcg_temp_new();
> + gen_read_greg({self.reg_tcg()}, {self.reg_num});
Do you need this read if it's a destination register?
> + """))
> + def log_write(self, f, tag):
> + f.write(code_fmt(f"""\
> + gen_log_greg_write(ctx, {self.reg_num}, {self.reg_tcg()});
> + """))
> + def analyze_write(self, f, tag, regno):
> + f.write(code_fmt(f"""\
> + ctx_log_greg_write(ctx, {self.reg_num});
> + """))
> +
> +class GuestSource(GuestRegister, Single, OldSource):
> + def decl_tcg(self, f, tag, regno):
> + self.decl_reg_num(f, regno);
> + self.gen_check_impl(f, regno)
> + f.write(code_fmt(f"""\
> + TCGv {self.reg_tcg()} = tcg_temp_new();
> + gen_read_greg({self.reg_tcg()}, {self.reg_num});
> + """))
> +
> +class GuestPairDest(GuestRegister, Pair, Dest):
> + def decl_tcg(self, f, tag, regno):
> + self.decl_reg_num(f, regno)
> + self.gen_check_impl(f, regno)
> + f.write(code_fmt(f"""\
> + TCGv_i64 {self.reg_tcg()} = tcg_temp_new_i64();
> + gen_read_greg_pair({self.reg_tcg()}, {self.reg_num});
Read needed?
> + """))
> + def log_write(self, f, tag):
> + f.write(code_fmt(f"""\
> + gen_log_greg_write_pair(ctx, {self.reg_num}, {self.reg_tcg()});
> + """))
> + def analyze_write(self, f, tag, regno):
> + f.write(code_fmt(f"""\
> + ctx_log_greg_write_pair(ctx, {self.reg_num});
> + """))
> +
> +class GuestPairSource(GuestRegister, Pair, OldSource):
> + def decl_tcg(self, f, tag, regno):
> + self.decl_reg_num(f, regno)
> + self.gen_check_impl(f, regno)
> + f.write(code_fmt(f"""\
> + TCGv_i64 {self.reg_tcg()} = tcg_temp_new_i64();
> + gen_read_greg_pair({self.reg_tcg()}, {self.reg_num});
> + """))
> +
> +class SystemDest(Register, Single, Dest):
> + def decl_tcg(self, f, tag, regno):
> + self.decl_reg_num(f, regno)
> + f.write(code_fmt(f"""\
> + TCGv {self.reg_tcg()} = tcg_temp_new();
> + gen_read_sreg({self.reg_tcg()}, {self.reg_num});
Read needed?
> + """))
> + def log_write(self, f, tag):
> + f.write(code_fmt(f"""\
> + gen_log_sreg_write(ctx, {self.reg_num}, {self.reg_tcg()});
> + """))
> + def analyze_write(self, f, tag, regno):
> + f.write(code_fmt(f"""\
> + ctx_log_sreg_write(ctx, {self.reg_num});
> + """))
> +
> +class SystemSource(Register, Single, OldSource):
> + def decl_tcg(self, f, tag, regno):
> + self.decl_reg_num(f, regno);
> + f.write(code_fmt(f"""\
> + TCGv {self.reg_tcg()} = tcg_temp_new();
> + gen_read_sreg({self.reg_tcg()}, {self.reg_num});
> + """))
> +
> +class SystemPairDest(Register, Pair, Dest):
> + def decl_tcg(self, f, tag, regno):
> + self.decl_reg_num(f, regno)
> + f.write(code_fmt(f"""\
> + TCGv_i64 {self.reg_tcg()} = tcg_temp_new_i64();
> + gen_read_sreg_pair({self.reg_tcg()}, {self.reg_num});
Read needed?
> + """))
> + def log_write(self, f, tag):
> + f.write(code_fmt(f"""\
> + gen_log_sreg_write_pair(ctx, {self.reg_num}, {self.reg_tcg()});
> + """))
> + def analyze_write(self, f, tag, regno):
> + f.write(code_fmt(f"""\
> + ctx_log_sreg_write_pair(ctx, {self.reg_num});
> + """))
> +
> +class SystemPairSource(Register, Pair, OldSource):
> + def decl_tcg(self, f, tag, regno):
> + self.decl_reg_num(f, regno)
> + f.write(code_fmt(f"""\
> + TCGv_i64 {self.reg_tcg()} = tcg_temp_new_i64();
> + gen_read_sreg_pair({self.reg_tcg()}, {self.reg_num});
> + """))
> +
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