According to RISC-V Cryptography Extensions Volume I. Version 1.0.1 Chapter 4.1
BIST alarm must be latched until polled at least once to enable software to
record its occurrence.

Signed-off-by: Saveliy Motov <saveliy.motov@syntacore.com>
---
 target/riscv/cpu.c | 3 +++
 target/riscv/cpu.h | 4 ++++
 target/riscv/csr.c | 7 ++++++-
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cca24b9f1f..a5724b2fca 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1046,6 +1046,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
     if (mcc->parent_phases.hold) {
         mcc->parent_phases.hold(obj, type);
     }
+
+    env->zkr_csr_is_read = false;
+
 #ifndef CONFIG_USER_ONLY
     env->misa_mxl = mcc->misa_mxl_max;
     env->priv = PRV_M;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 97713681cb..7fc36ae7ba 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -250,6 +250,10 @@ struct CPUArchState {
     target_ulong excp_uw2;
     /* sw check code for sw check exception */
     target_ulong sw_check_code;
+
+    /* ZKR state */
+    bool zkr_csr_is_read;
+
 #ifdef CONFIG_USER_ONLY
     uint32_t elf_flags;
 #endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index afb7544f07..3af4f69698 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -5152,10 +5152,15 @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 {
     target_ulong rval;
 
-    rval = riscv_new_csr_seed(new_value, write_mask);
+    if (env->zkr_csr_is_read) {
+        rval = riscv_new_csr_seed(new_value, write_mask);
+    } else {
+        rval = SEED_OPST_BIST;
+    }
 
     if (ret_value) {
         *ret_value = rval;
+        env->zkr_csr_is_read = true;
     }
 
     return RISCV_EXCP_NONE;
-- 
2.34.1