riscv: Fix Zkr bugs

[PATCH 0/2] riscv: Fix Zkr bugs

Saveliy Motov posted 2 patches 11 months, 2 weeks ago

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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20250227144200.69270-1-saveliy.motov@syntacore.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/cpu.c      |  3 +++
target/riscv/cpu.h      |  4 ++++
target/riscv/cpu_bits.h | 10 +++++-----
target/riscv/csr.c      |  7 ++++++-
4 files changed, 18 insertions(+), 6 deletions(-)

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[PATCH 0/2] riscv: Fix Zkr bugs

Posted by Saveliy Motov 11 months, 2 weeks ago

This series fixes Zkr extension bugs.
- Fix Zkr CSR first reading
- Fix Zkr higher bits in riscv64 machine


Saveliy Motov (2):
  target/riscv/csr.c: Fix first Zkr CSR reading
  target/riscv/cpu_bits.h: Fix [63:32] bits in Zkr seed csr

 target/riscv/cpu.c      |  3 +++
 target/riscv/cpu.h      |  4 ++++
 target/riscv/cpu_bits.h | 10 +++++-----
 target/riscv/csr.c      |  7 ++++++-
 4 files changed, 18 insertions(+), 6 deletions(-)

-- 
2.34.1