target/loongarch/cpu.c | 152 +++++++++++++++++---- target/loongarch/helper.h | 22 +-- target/loongarch/tcg/csr_helper.c | 2 +- target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 8 +- target/loongarch/tcg/insn_trans/trans_shift.c.inc | 4 +- target/loongarch/tcg/iocsr_helper.c | 20 +-- target/loongarch/tcg/op_helper.c | 4 +- target/loongarch/tcg/tlb_helper.c | 2 +- target/loongarch/tcg/translate.c | 5 +- 9 files changed, 155 insertions(+), 64 deletions(-)
Hi all,
This series is a collection of small fixes I made to TCG for
LoongArch32.
There are still many thing broken, especially on CSRs. More
series following. However this is sufficient to boot 32bit
kernel.
Thanks for revivewing!
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
Changes in v2:
- Addressing minor review comments
- Don't create 32bit vairant, simply allow 32bit CPU on qemu-loongarch64
- Link to v1: https://lore.kernel.org/r/20241222-la32-fixes1-v1-0-8c62b7e594db@flygoat.com
---
Jiaxun Yang (9):
target/loongarch: Enable rotr.w/rotri.w for LoongArch32
target/loongarch: Fix address generation for gen_sc
target/loongarch: Fix PGD CSR for LoongArch32
target/loongarch: Perform sign extension for IOCSR reads
target/loongarch: Use target_ulong for iocsrrd helper results
target/loongarch: Fix some modifiers for log formatting
target/loongarch: Use target_ulong for CSR helpers
target/loongarch: Fix load type for gen_ll
target/loongarch: Introduce max32 CPU type
target/loongarch/cpu.c | 152 +++++++++++++++++----
target/loongarch/helper.h | 22 +--
target/loongarch/tcg/csr_helper.c | 2 +-
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 8 +-
target/loongarch/tcg/insn_trans/trans_shift.c.inc | 4 +-
target/loongarch/tcg/iocsr_helper.c | 20 +--
target/loongarch/tcg/op_helper.c | 4 +-
target/loongarch/tcg/tlb_helper.c | 2 +-
target/loongarch/tcg/translate.c | 5 +-
9 files changed, 155 insertions(+), 64 deletions(-)
---
base-commit: 65cb7129f4160c7e07a0da107f888ec73ae96776
change-id: 20241222-la32-fixes1-368cc14d0986
Best regards,
--
Jiaxun Yang <jiaxun.yang@flygoat.com>
On 2025/2/25 上午8:40, Jiaxun Yang wrote: > Hi all, > > This series is a collection of small fixes I made to TCG for > LoongArch32. > > There are still many thing broken, especially on CSRs. More > series following. However this is sufficient to boot 32bit > kernel. Is there any product introduction about LoongArch32 board? such as MMU type, memory type(DDR or SRAM), interrupt controller type. Regards Bibo Mao > > Thanks for revivewing! > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > Changes in v2: > - Addressing minor review comments > - Don't create 32bit vairant, simply allow 32bit CPU on qemu-loongarch64 > - Link to v1: https://lore.kernel.org/r/20241222-la32-fixes1-v1-0-8c62b7e594db@flygoat.com > > --- > Jiaxun Yang (9): > target/loongarch: Enable rotr.w/rotri.w for LoongArch32 > target/loongarch: Fix address generation for gen_sc > target/loongarch: Fix PGD CSR for LoongArch32 > target/loongarch: Perform sign extension for IOCSR reads > target/loongarch: Use target_ulong for iocsrrd helper results > target/loongarch: Fix some modifiers for log formatting > target/loongarch: Use target_ulong for CSR helpers > target/loongarch: Fix load type for gen_ll > target/loongarch: Introduce max32 CPU type > > target/loongarch/cpu.c | 152 +++++++++++++++++---- > target/loongarch/helper.h | 22 +-- > target/loongarch/tcg/csr_helper.c | 2 +- > target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 8 +- > target/loongarch/tcg/insn_trans/trans_shift.c.inc | 4 +- > target/loongarch/tcg/iocsr_helper.c | 20 +-- > target/loongarch/tcg/op_helper.c | 4 +- > target/loongarch/tcg/tlb_helper.c | 2 +- > target/loongarch/tcg/translate.c | 5 +- > 9 files changed, 155 insertions(+), 64 deletions(-) > --- > base-commit: 65cb7129f4160c7e07a0da107f888ec73ae96776 > change-id: 20241222-la32-fixes1-368cc14d0986 > > Best regards, >
在2025年2月25日二月 上午8:50，bibo mao写道：
> On 2025/2/25 上午8:40, Jiaxun Yang wrote:
>> Hi all,
>>
>> This series is a collection of small fixes I made to TCG for
>> LoongArch32.
>>
>> There are still many thing broken, especially on CSRs. More
>> series following. However this is sufficient to boot 32bit
>> kernel.
> Is there any product introduction about LoongArch32 board? such as MMU
> type, memory type(DDR or SRAM), interrupt controller type.
Sure, for LoongArch32 the most accessible board at the moment is chiplap FPGA [1].
There are also some ASIC designs (BaiXing Project) based on chiplab.
Long in short:
- MMU: PG style
- Mmeory: DDR
- Interrupt controller: custom (Loongson-1C like) connected to CPU's
int pin.
Thanks
[1]: https://gitee.com/loongson-edu/chiplab
>
> Regards
> Bibo Mao
>>
--
- Jiaxun
On 2025/2/25 下午8:08, Jiaxun Yang wrote: > > > 在2025年2月25日二月 上午8:50，bibo mao写道： >> On 2025/2/25 上午8:40, Jiaxun Yang wrote: >>> Hi all, >>> >>> This series is a collection of small fixes I made to TCG for >>> LoongArch32. >>> >>> There are still many thing broken, especially on CSRs. More >>> series following. However this is sufficient to boot 32bit >>> kernel. >> Is there any product introduction about LoongArch32 board? such as MMU >> type, memory type(DDR or SRAM), interrupt controller type. > > Sure, for LoongArch32 the most accessible board at the moment is chiplap FPGA [1]. > > There are also some ASIC designs (BaiXing Project) based on chiplab. > > Long in short: > > - MMU: PG style > - Mmeory: DDR > - Interrupt controller: custom (Loongson-1C like) connected to CPU's > int pin. Thanks for the information, Would you like to emulate LoongArch32 chiplap FPGA board in qemu side or other LoongArch32 boards? Regards Bibo Mao > > Thanks > > [1]: https://gitee.com/loongson-edu/chiplab > >> >> Regards >> Bibo Mao >>> > >
在2025年2月25日二月 下午12:33，bibo mao写道： > On 2025/2/25 下午8:08, Jiaxun Yang wrote: >> >> >> 在2025年2月25日二月 上午8:50，bibo mao写道： >>> On 2025/2/25 上午8:40, Jiaxun Yang wrote: >>>> Hi all, >>>> >>>> This series is a collection of small fixes I made to TCG for >>>> LoongArch32. >>>> >>>> There are still many thing broken, especially on CSRs. More >>>> series following. However this is sufficient to boot 32bit >>>> kernel. >>> Is there any product introduction about LoongArch32 board? such as MMU >>> type, memory type(DDR or SRAM), interrupt controller type. >> >> Sure, for LoongArch32 the most accessible board at the moment is chiplap FPGA [1]. >> >> There are also some ASIC designs (BaiXing Project) based on chiplab. >> >> Long in short: >> >> - MMU: PG style >> - Mmeory: DDR >> - Interrupt controller: custom (Loongson-1C like) connected to CPU's >> int pin. > Thanks for the information, Would you like to emulate LoongArch32 > chiplap FPGA board in qemu side or other LoongArch32 boards? My plan is to use current virt machine (with EXTIOI and so on) for LoongArch32, it is trivial to bring up in kernel and give us a lot more flexibility rather than emulating an actual board. Thanks - Jiaxun > > Regards > Bibo Mao >> >> Thanks >> >> [1]: https://gitee.com/loongson-edu/chiplab >> >>> >>> Regards >>> Bibo Mao >>>> >> >> -- - Jiaxun
On 2025/2/27 下午6:44, Jiaxun Yang wrote: > > > 在2025年2月25日二月 下午12:33，bibo mao写道： >> On 2025/2/25 下午8:08, Jiaxun Yang wrote: >>> >>> >>> 在2025年2月25日二月 上午8:50，bibo mao写道： >>>> On 2025/2/25 上午8:40, Jiaxun Yang wrote: >>>>> Hi all, >>>>> >>>>> This series is a collection of small fixes I made to TCG for >>>>> LoongArch32. >>>>> >>>>> There are still many thing broken, especially on CSRs. More >>>>> series following. However this is sufficient to boot 32bit >>>>> kernel. >>>> Is there any product introduction about LoongArch32 board? such as MMU >>>> type, memory type(DDR or SRAM), interrupt controller type. >>> >>> Sure, for LoongArch32 the most accessible board at the moment is chiplap FPGA [1]. >>> >>> There are also some ASIC designs (BaiXing Project) based on chiplab. >>> >>> Long in short: >>> >>> - MMU: PG style >>> - Mmeory: DDR >>> - Interrupt controller: custom (Loongson-1C like) connected to CPU's >>> int pin. >> Thanks for the information, Would you like to emulate LoongArch32 >> chiplap FPGA board in qemu side or other LoongArch32 boards? > > My plan is to use current virt machine (with EXTIOI and so on) for > LoongArch32, it is trivial to bring up in kernel and give us a lot more > flexibility rather than emulating an actual board. virt machine is mainly for kvm board. If it is used as LoongArch32 board, there is no much benefit to add bunch of code in kernel and qemu to emulate non-exist board, on the contrast it is hard to maintain. In LoongArch community There are many cases posting code in one time, disappear and lose maintenance :( Regards Bibo MAo > > Thanks > - Jiaxun > >> >> Regards >> Bibo Mao >>> >>> Thanks >>> >>> [1]: https://gitee.com/loongson-edu/chiplab >>> >>>> >>>> Regards >>>> Bibo Mao >>>>> >>> >>> >
在2025年2月27日二月 下午12:21，bibo mao写道： [...] >>>> int pin. >>> Thanks for the information, Would you like to emulate LoongArch32 >>> chiplap FPGA board in qemu side or other LoongArch32 boards? >> >> My plan is to use current virt machine (with EXTIOI and so on) for >> LoongArch32, it is trivial to bring up in kernel and give us a lot more >> flexibility rather than emulating an actual board. > virt machine is mainly for kvm board. If it is used as LoongArch32 > board, there is no much benefit to add bunch of code in kernel and qemu > to emulate non-exist board, on the contrast it is hard to maintain. Actually, it's 8 lines of code machine level code in my local tree to bring up. Adding a new board will increase maintain burden as well. Also to note that LoongArch32 TCG work is also for qemu user. riscv32, arm32 are all sharing same virt board as well. QEMU is not only serving KVM but also other users trying to evaluate and test on the platform. For kernel drivers are already here, still, just a couple of Kconfig changes, you can preview here [1]. > > In LoongArch community There are many cases posting code in one time, > disappear and lose maintenance :( Yep, for hobbyists it's hard to sustain our effort :-( we are all trying our best to contribute. I can potentially spare more time in Q2 to make everything work. Thanks [1]: https://github.com/FlyGoat/linux/tree/b4/la32 -- - Jiaxun
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