Hi; this pullreq contains a new board model npcm845-evb, plus some
more minor cleanups, refactorings and a few bugfixes.
thanks
-- PMM
The following changes since commit 40efe733e10cc00e4fb4f9f5790a28e744e63c62:
Merge tag 'pull-tcg-20250215-3' of https://gitlab.com/rth7680/qemu into staging (2025-02-19 08:36:45 +0800)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250220
for you to fetch changes up to 1c3169179b8242866316108386800379c4e22974:
docs/system/arm: Add Description for NPCM8XX SoC (2025-02-20 15:22:22 +0000)
----------------------------------------------------------------
target-arm queue:
* Fix some incorrect syndrome values in various sysreg traps
* Clean up sysreg trap code to avoid similar future bugs
* Make boards/SoCs using a9mpcore and a15mpcore objects specify
number of GIC interrupts explicitly
* Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX
* target/arm: Use uint32_t in t32_expandimm_imm()
* New board model: NPCM845 Evaluation board "npcm845-evb"
----------------------------------------------------------------
Bernhard Beschow (1):
Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX
Hao Wu (17):
roms: Update vbootrom to 1287b6e
pc-bios: Add NPCM8XX vBootrom
hw/ssi: Make flash size a property in NPCM7XX FIU
hw/misc: Rename npcm7xx_gcr to npcm_gcr
hw/misc: Move NPCM7XX GCR to NPCM GCR
hw/misc: Add nr_regs and cold_reset_values to NPCM GCR
hw/misc: Add support for NPCM8XX GCR
hw/misc: Store DRAM size in NPCM8XX GCR Module
hw/misc: Support 8-bytes memop in NPCM GCR module
hw/misc: Rename npcm7xx_clk to npcm_clk
hw/misc: Move NPCM7XX CLK to NPCM CLK
hw/misc: Add nr_regs and cold_reset_values to NPCM CLK
hw/misc: Support NPCM8XX CLK Module Registers
hw/net: Add NPCM8XX PCS Module
hw/arm: Add NPCM8XX SoC
hw/arm: Add NPCM845 Evaluation board
docs/system/arm: Add Description for NPCM8XX SoC
Peter Maydell (14):
target/arm: Report correct syndrome for UNDEFINED CNTPS_*_EL1 from EL2 and NS EL1
target/arm: Report correct syndrome for UNDEFINED AT ops with wrong NSE, NS
target/arm: Report correct syndrome for UNDEFINED S1E2 AT ops at EL3
target/arm: Report correct syndrome for UNDEFINED LOR sysregs when NS=0
target/arm: Make CP_ACCESS_TRAPs to AArch32 EL3 be Monitor traps
hw/intc/arm_gicv3_cpuif: Don't downgrade monitor traps for AArch32 EL3
target/arm: Honour SDCR.TDCC and SCR.TERR in AArch32 EL3 non-Monitor modes
hw/intc/arm_gicv3_cpuif(): Remove redundant tests of is_a64()
target/arm: Support CP_ACCESS_TRAP_EL1 as a CPAccessResult
target/arm: Use CP_ACCESS_TRAP_EL1 for traps that are always to EL1
target/arm: Use TRAP_UNCATEGORIZED for XScale CPAR traps
target/arm: Remove CP_ACCESS_TRAP handling
target/arm: Rename CP_ACCESS_TRAP_UNCATEGORIZED to CP_ACCESS_UNDEFINED
target/arm: Correct errors in WFI/WFE trapping
Philippe Mathieu-Daudé (8):
hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition
hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs
hw/arm/realview: Specify explicitly the GIC has 64 external IRQs
hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL
hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs
hw/arm/vexpress: Specify explicitly the GIC has 64 external IRQs
hw/arm/highbank: Specify explicitly the GIC has 128 external IRQs
hw/cpu/arm_mpcore: Remove default values for GIC external IRQs
Stephen Longfield (1):
target/arm: Use uint32_t in t32_expandimm_imm()
MAINTAINERS | 1 +
docs/system/arm/nuvoton.rst | 27 +-
configs/devices/aarch64-softmmu/default.mak | 1 +
include/hw/arm/npcm7xx.h | 8 +-
include/hw/arm/npcm8xx.h | 127 ++++
include/hw/misc/{npcm7xx_clk.h => npcm_clk.h} | 47 +-
include/hw/misc/{npcm7xx_gcr.h => npcm_gcr.h} | 29 +-
include/hw/net/npcm_pcs.h | 42 ++
include/hw/ssi/npcm7xx_fiu.h | 1 +
target/arm/cpregs.h | 15 +-
target/arm/cpu.h | 6 +
hw/arm/exynos4210.c | 10 +-
hw/arm/highbank.c | 8 +-
hw/arm/npcm7xx.c | 6 +
hw/arm/npcm8xx.c | 805 ++++++++++++++++++++++++++
hw/arm/npcm8xx_boards.c | 254 ++++++++
hw/arm/realview.c | 11 +-
hw/arm/vexpress.c | 7 +-
hw/arm/xilinx_zynq.c | 43 +-
hw/cpu/a15mpcore.c | 18 +-
hw/cpu/a9mpcore.c | 18 +-
hw/intc/arm_gicv3_cpuif.c | 15 +-
hw/misc/npcm7xx_gcr.c | 264 ---------
hw/misc/{npcm7xx_clk.c => npcm_clk.c} | 235 ++++++--
hw/misc/npcm_gcr.c | 482 +++++++++++++++
hw/net/npcm_pcs.c | 410 +++++++++++++
hw/ssi/npcm7xx_fiu.c | 16 +-
target/arm/debug_helper.c | 5 +-
target/arm/helper.c | 75 ++-
target/arm/tcg/op_helper.c | 71 ++-
target/arm/tcg/translate.c | 2 +-
hw/arm/Kconfig | 19 +-
hw/arm/meson.build | 1 +
hw/misc/meson.build | 4 +-
hw/misc/trace-events | 12 +-
hw/net/meson.build | 1 +
hw/net/trace-events | 4 +-
hw/usb/Kconfig | 4 +
hw/usb/meson.build | 2 +-
pc-bios/README | 8 +-
pc-bios/meson.build | 1 +
pc-bios/npcm7xx_bootrom.bin | Bin 768 -> 768 bytes
pc-bios/npcm8xx_bootrom.bin | Bin 0 -> 608 bytes
roms/Makefile | 6 +
roms/vbootrom | 2 +-
45 files changed, 2626 insertions(+), 497 deletions(-)
create mode 100644 include/hw/arm/npcm8xx.h
rename include/hw/misc/{npcm7xx_clk.h => npcm_clk.h} (83%)
rename include/hw/misc/{npcm7xx_gcr.h => npcm_gcr.h} (76%)
create mode 100644 include/hw/net/npcm_pcs.h
create mode 100644 hw/arm/npcm8xx.c
create mode 100644 hw/arm/npcm8xx_boards.c
delete mode 100644 hw/misc/npcm7xx_gcr.c
rename hw/misc/{npcm7xx_clk.c => npcm_clk.c} (82%)
create mode 100644 hw/misc/npcm_gcr.c
create mode 100644 hw/net/npcm_pcs.c
create mode 100644 pc-bios/npcm8xx_bootrom.bin