Log FIFO use (availability and depth).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/char/pl011.c | 10 ++++++----
hw/char/trace-events | 7 ++++---
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index bcd516d682d..148a7d0dc60 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -185,7 +185,7 @@ static void pl011_fifo_rx_put(void *opaque, uint32_t value)
s->read_fifo[slot] = value;
s->read_count++;
s->flags &= ~PL011_FLAG_RXFE;
- trace_pl011_fifo_rx_put(value, s->read_count);
+ trace_pl011_fifo_rx_put(value, s->read_count, pipe_depth);
if (s->read_count == pipe_depth) {
trace_pl011_fifo_rx_full();
s->flags |= PL011_FLAG_RXFF;
@@ -248,12 +248,13 @@ static void pl011_write_txdata(PL011State *s, uint8_t data)
static uint32_t pl011_read_rxdata(PL011State *s)
{
uint32_t c;
+ unsigned fifo_depth = pl011_get_fifo_depth(s);
s->flags &= ~PL011_FLAG_RXFF;
c = s->read_fifo[s->read_pos];
if (s->read_count > 0) {
s->read_count--;
- s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1);
+ s->read_pos = (s->read_pos + 1) & (fifo_depth - 1);
}
if (s->read_count == 0) {
s->flags |= PL011_FLAG_RXFE;
@@ -261,7 +262,7 @@ static uint32_t pl011_read_rxdata(PL011State *s)
if (s->read_count == s->read_trigger - 1) {
s->int_level &= ~INT_RX;
}
- trace_pl011_read_fifo(s->read_count);
+ trace_pl011_read_fifo(s->read_count, fifo_depth);
s->rsr = c >> 8;
pl011_update(s);
qemu_chr_fe_accept_input(&s->chr);
@@ -496,12 +497,13 @@ static int pl011_can_receive(void *opaque)
if (!(s->cr & CR_RXE)) {
qemu_log_mask(LOG_GUEST_ERROR, "PL011 reading data on disabled TX UART\n");
}
- trace_pl011_can_receive(s->lcr, s->read_count, r);
+ trace_pl011_can_receive(s->lcr, s->read_count, fifo_depth, fifo_available);
return r;
}
static void pl011_receive(void *opaque, const uint8_t *buf, int size)
{
+ trace_pl011_receive(size);
/*
* In loopback mode, the RX input signal is internally disconnected
* from the entire receiving logics; thus, all inputs are ignored,
diff --git a/hw/char/trace-events b/hw/char/trace-events
index b2e3d25ae34..05a33036c12 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -60,12 +60,13 @@ imx_serial_put_data(const char *chrname, uint32_t value) "%s: 0x%" PRIx32
# pl011.c
pl011_irq_state(int level) "irq state %d"
pl011_read(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s"
-pl011_read_fifo(int read_count) "FIFO read, read_count now %d"
+pl011_read_fifo(unsigned rx_fifo_used, size_t rx_fifo_depth) "RX FIFO read, used %u/%zu"
pl011_write(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s"
-pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count %d returning %d"
-pl011_fifo_rx_put(uint32_t c, int read_count) "new char 0x%02x read_count now %d"
+pl011_can_receive(uint32_t lcr, unsigned rx_fifo_used, size_t rx_fifo_depth, unsigned rx_fifo_available) "LCR 0x%02x, RX FIFO used %u/%zu, can_receive %u chars"
+pl011_fifo_rx_put(uint32_t c, unsigned read_count, size_t rx_fifo_depth) "RX FIFO push char [0x%02x] %d/%zu depth used"
pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set"
pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd, uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd: %" PRIu32 ")"
+pl011_receive(int size) "recv %d chars"
# cmsdk-apb-uart.c
cmsdk_apb_uart_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB UART read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
--
2.47.1
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> Log FIFO use (availability and depth).
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
> ---
> hw/char/pl011.c | 10 ++++++----
> hw/char/trace-events | 7 ++++---
> 2 files changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/hw/char/pl011.c b/hw/char/pl011.c
> index bcd516d682d..148a7d0dc60 100644
> --- a/hw/char/pl011.c
> +++ b/hw/char/pl011.c
> @@ -185,7 +185,7 @@ static void pl011_fifo_rx_put(void *opaque, uint32_t value)
> s->read_fifo[slot] = value;
> s->read_count++;
> s->flags &= ~PL011_FLAG_RXFE;
> - trace_pl011_fifo_rx_put(value, s->read_count);
> + trace_pl011_fifo_rx_put(value, s->read_count, pipe_depth);
> if (s->read_count == pipe_depth) {
> trace_pl011_fifo_rx_full();
> s->flags |= PL011_FLAG_RXFF;
> @@ -248,12 +248,13 @@ static void pl011_write_txdata(PL011State *s, uint8_t data)
> static uint32_t pl011_read_rxdata(PL011State *s)
> {
> uint32_t c;
> + unsigned fifo_depth = pl011_get_fifo_depth(s);
>
> s->flags &= ~PL011_FLAG_RXFF;
> c = s->read_fifo[s->read_pos];
> if (s->read_count > 0) {
> s->read_count--;
> - s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1);
> + s->read_pos = (s->read_pos + 1) & (fifo_depth - 1);
> }
> if (s->read_count == 0) {
> s->flags |= PL011_FLAG_RXFE;
> @@ -261,7 +262,7 @@ static uint32_t pl011_read_rxdata(PL011State *s)
> if (s->read_count == s->read_trigger - 1) {
> s->int_level &= ~INT_RX;
> }
> - trace_pl011_read_fifo(s->read_count);
> + trace_pl011_read_fifo(s->read_count, fifo_depth);
> s->rsr = c >> 8;
> pl011_update(s);
> qemu_chr_fe_accept_input(&s->chr);
> @@ -496,12 +497,13 @@ static int pl011_can_receive(void *opaque)
> if (!(s->cr & CR_RXE)) {
> qemu_log_mask(LOG_GUEST_ERROR, "PL011 reading data on disabled TX UART\n");
> }
> - trace_pl011_can_receive(s->lcr, s->read_count, r);
> + trace_pl011_can_receive(s->lcr, s->read_count, fifo_depth, fifo_available);
> return r;
> }
>
> static void pl011_receive(void *opaque, const uint8_t *buf, int size)
> {
> + trace_pl011_receive(size);
> /*
> * In loopback mode, the RX input signal is internally disconnected
> * from the entire receiving logics; thus, all inputs are ignored,
> diff --git a/hw/char/trace-events b/hw/char/trace-events
> index b2e3d25ae34..05a33036c12 100644
> --- a/hw/char/trace-events
> +++ b/hw/char/trace-events
> @@ -60,12 +60,13 @@ imx_serial_put_data(const char *chrname, uint32_t value) "%s: 0x%" PRIx32
> # pl011.c
> pl011_irq_state(int level) "irq state %d"
> pl011_read(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s"
> -pl011_read_fifo(int read_count) "FIFO read, read_count now %d"
> +pl011_read_fifo(unsigned rx_fifo_used, size_t rx_fifo_depth) "RX FIFO read, used %u/%zu"
> pl011_write(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s"
> -pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count %d returning %d"
> -pl011_fifo_rx_put(uint32_t c, int read_count) "new char 0x%02x read_count now %d"
> +pl011_can_receive(uint32_t lcr, unsigned rx_fifo_used, size_t rx_fifo_depth, unsigned rx_fifo_available) "LCR 0x%02x, RX FIFO used %u/%zu, can_receive %u chars"
> +pl011_fifo_rx_put(uint32_t c, unsigned read_count, size_t rx_fifo_depth) "RX FIFO push char [0x%02x] %d/%zu depth used"
> pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set"
> pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd, uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd: %" PRIu32 ")"
> +pl011_receive(int size) "recv %d chars"
>
> # cmsdk-apb-uart.c
> cmsdk_apb_uart_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB UART read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
> --
> 2.47.1
>
--
Philippe Mathieu-Daudé <philmd@linaro.org> writes: > Log FIFO use (availability and depth). > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> -- Alex Bennée Virtualisation Tech Lead @ Linaro
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