[PULL v2.5 00/27] tcg patch queue
[PULL 00/23] tcg patch queue
1
v2: Fix target/loongarch printf formats for vaddr
1
The following changes since commit 98c7362b1efe651327385a25874a73e008c6549e:
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Include two more reviewed patches.
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2
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This time with actual pull urls. :-/
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Merge tag 'accel-cpus-20250306' of https://github.com/philmd/qemu into staging (2025-03-07 07:39:49 +0800)
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r~
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The following changes since commit db7aa99ef894e88fc5eedf02ca2579b8c344b2ec:
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11
Merge tag 'hw-misc-20250216' of https://github.com/philmd/qemu into staging (2025-02-16 20:48:06 -0500)
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are available in the Git repository at:
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are available in the Git repository at:
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15
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215-2
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250308
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for you to fetch changes up to a39bdd0f4ba96fcbb6b5bcb6e89591d2b24f52eb:
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for you to fetch changes up to 9e2080766f037857fc366012aaefd6fead0a75f9:
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19
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 (2025-02-17 09:52:07 -0800)
11
accel/tcg: Build tcg-runtime-gvec.c once (2025-03-08 10:06:48 -0800)
20
12
21
----------------------------------------------------------------
13
----------------------------------------------------------------
22
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
14
include/qemu: Tidy atomic128 headers.
23
tcg: Cleanups after disallowing 64-on-32
15
include/exec: Split out cpu-interrupt.h
24
tcg: Introduce constraint for zero register
16
include/exec: Split many tlb_* declarations to cputlb.h
25
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
17
include/accel/tcg: Split out getpc.h
26
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
18
accel/tcg: system: Compile some files once
27
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
19
linux-user/main: Allow setting tb-size
28
linux-user: Fix alignment when unmapping excess reservation
29
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
30
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
31
target/sparc: fake UltraSPARC T1 PCR and PIC registers
32
20
33
----------------------------------------------------------------
21
----------------------------------------------------------------
34
Andreas Schwab (1):
22
Ilya Leoshkevich (1):
35
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
23
linux-user/main: Allow setting tb-size
36
24
37
Artyom Tarasenko (1):
25
Philippe Mathieu-Daudé (11):
38
target/sparc: fake UltraSPARC T1 PCR and PIC registers
26
accel/tcg: Restrict CPU_TLB_DYN_*_BITS definitions to accel/tcg/
27
exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h'
28
exec: Declare tlb_set_page_full() in 'exec/cputlb.h'
29
exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h'
30
exec: Declare tlb_set_page() in 'exec/cputlb.h'
31
exec: Declare tlb_hit*() in 'exec/cputlb.h'
32
exec: Declare tlb_flush*() in 'exec/cputlb.h'
33
accel/tcg: Restrict GETPC_ADJ to 'tb-internal.h'
34
qemu/atomic: Rename atomic128-cas.h headers using .h.inc suffix
35
qemu/atomic: Rename atomic128-ldst.h headers using .h.inc suffix
36
qemu/atomic128: Include missing 'qemu/atomic.h' header
39
37
40
Fabiano Rosas (1):
38
Richard Henderson (11):
41
elfload: Fix alignment when unmapping excess reservation
39
include/exec: Move TARGET_PAGE_{SIZE,MASK,BITS} to target_page.h
40
include/exec: Split out exec/cpu-interrupt.h
41
accel/tcg: Compile watchpoint.c once
42
system: Build watchpoint.c once
43
accel/tcg: Build tcg-accel-ops.c once
44
accel/tcg: Build tcg-accel-ops-icount.c once
45
accel/tcg: Build tcg-accel-ops-rr.c once
46
accel/tcg: Build tcg-accel-ops-mttcg.c once
47
accel/tcg: Split out getpc.h
48
accel/tcg: Build tcg-runtime.c once
49
accel/tcg: Build tcg-runtime-gvec.c once
42
50
43
Mikael Szreder (2):
51
accel/tcg/internal-common.h | 2 +
44
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
52
accel/tcg/tb-internal.h | 40 +++-
45
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
53
host/include/aarch64/host/atomic128-cas.h | 2 +-
54
include/accel/tcg/getpc.h | 24 ++
55
include/exec/cpu-all.h | 97 +-------
56
include/exec/cpu-defs.h | 26 --
57
include/exec/cpu-interrupt.h | 70 ++++++
58
include/exec/cputlb.h | 263 ++++++++++++++++++++-
59
include/exec/exec-all.h | 262 +-------------------
60
include/exec/poison.h | 17 --
61
include/exec/ram_addr.h | 1 +
62
include/exec/target_page.h | 58 ++++-
63
include/qemu/atomic128.h | 5 +-
64
accel/tcg/cputlb.c | 23 ++
65
accel/tcg/tcg-accel-ops-icount.c | 2 +-
66
accel/tcg/tcg-accel-ops-mttcg.c | 1 -
67
accel/tcg/tcg-accel-ops-rr.c | 2 +-
68
accel/tcg/tcg-accel-ops.c | 2 +-
69
accel/tcg/tcg-runtime-gvec.c | 1 -
70
accel/tcg/tcg-runtime.c | 8 +-
71
accel/tcg/watchpoint.c | 5 +-
72
cpu-target.c | 1 +
73
hw/intc/armv7m_nvic.c | 2 +-
74
hw/ppc/spapr_nested.c | 1 +
75
hw/sh4/sh7750.c | 1 +
76
linux-user/main.c | 12 +
77
page-target.c | 18 --
78
page-vary-target.c | 2 -
79
system/physmem.c | 1 +
80
system/watchpoint.c | 3 +-
81
target/alpha/helper.c | 2 +-
82
target/alpha/sys_helper.c | 2 +-
83
target/arm/helper.c | 1 +
84
target/arm/tcg/tlb-insns.c | 2 +-
85
target/avr/helper.c | 2 +-
86
target/hppa/mem_helper.c | 1 +
87
target/i386/helper.c | 2 +-
88
target/i386/machine.c | 2 +-
89
target/i386/tcg/fpu_helper.c | 2 +-
90
target/i386/tcg/misc_helper.c | 2 +-
91
target/i386/tcg/system/excp_helper.c | 2 +-
92
target/i386/tcg/system/misc_helper.c | 2 +-
93
target/i386/tcg/system/svm_helper.c | 2 +-
94
target/loongarch/tcg/csr_helper.c | 2 +-
95
target/loongarch/tcg/tlb_helper.c | 1 +
96
target/m68k/helper.c | 1 +
97
target/microblaze/helper.c | 2 +-
98
target/microblaze/mmu.c | 2 +-
99
target/mips/system/cp0.c | 2 +-
100
target/mips/tcg/system/cp0_helper.c | 2 +-
101
target/mips/tcg/system/tlb_helper.c | 1 +
102
target/openrisc/mmu.c | 2 +-
103
target/openrisc/sys_helper.c | 1 +
104
target/ppc/helper_regs.c | 2 +-
105
target/ppc/misc_helper.c | 1 +
106
target/ppc/mmu_helper.c | 1 +
107
target/riscv/cpu_helper.c | 1 +
108
target/riscv/csr.c | 1 +
109
target/riscv/op_helper.c | 1 +
110
target/riscv/pmp.c | 2 +-
111
target/rx/cpu.c | 2 +-
112
target/s390x/gdbstub.c | 2 +-
113
target/s390x/sigp.c | 1 +
114
target/s390x/tcg/excp_helper.c | 1 +
115
target/s390x/tcg/mem_helper.c | 1 +
116
target/s390x/tcg/misc_helper.c | 1 +
117
target/sh4/helper.c | 1 +
118
target/sparc/ldst_helper.c | 1 +
119
target/sparc/mmu_helper.c | 2 +-
120
target/tricore/helper.c | 2 +-
121
target/xtensa/helper.c | 2 +-
122
target/xtensa/mmu_helper.c | 1 +
123
accel/tcg/meson.build | 14 +-
124
.../{atomic128-ldst.h => atomic128-ldst.h.inc} | 0
125
.../host/{atomic128-cas.h => atomic128-cas.h.inc} | 0
126
.../{atomic128-ldst.h => atomic128-ldst.h.inc} | 0
127
.../{atomic128-ldst.h => atomic128-ldst.h.inc} | 0
128
.../{atomic128-ldst.h => atomic128-ldst.h.inc} | 2 +-
129
.../x86_64/host/load-extract-al16-al8.h.inc | 2 +-
130
system/meson.build | 2 +-
131
80 files changed, 552 insertions(+), 486 deletions(-)
132
create mode 100644 include/accel/tcg/getpc.h
133
create mode 100644 include/exec/cpu-interrupt.h
134
rename host/include/aarch64/host/{atomic128-ldst.h => atomic128-ldst.h.inc} (100%)
135
rename host/include/generic/host/{atomic128-cas.h => atomic128-cas.h.inc} (100%)
136
rename host/include/generic/host/{atomic128-ldst.h => atomic128-ldst.h.inc} (100%)
137
rename host/include/loongarch64/host/{atomic128-ldst.h => atomic128-ldst.h.inc} (100%)
138
rename host/include/x86_64/host/{atomic128-ldst.h => atomic128-ldst.h.inc} (96%)
46
139
47
Richard Henderson (22):
48
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
49
tcg: Remove TCG_OVERSIZED_GUEST
50
tcg: Drop support for two address registers in gen_ldst
51
tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
52
tcg/arm: Drop addrhi from prepare_host_addr
53
tcg/i386: Drop addrhi from prepare_host_addr
54
tcg/mips: Drop addrhi from prepare_host_addr
55
tcg/ppc: Drop addrhi from prepare_host_addr
56
tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
57
plugins: Fix qemu_plugin_read_memory_vaddr parameters
58
accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
59
target/loongarch: Use VADDR_PRIx for logging pc_next
60
include/exec: Change vaddr to uintptr_t
61
include/exec: Use uintptr_t in CPUTLBEntry
62
tcg: Introduce the 'z' constraint for a hardware zero register
63
tcg/aarch64: Use 'z' constraint
64
tcg/loongarch64: Use 'z' constraint
65
tcg/mips: Use 'z' constraint
66
tcg/riscv: Use 'z' constraint
67
tcg/sparc64: Use 'z' constraint
68
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
69
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
70
71
include/exec/tlb-common.h | 10 +-
72
include/exec/vaddr.h | 16 +-
73
include/qemu/atomic.h | 18 +-
74
include/tcg/oversized-guest.h | 23 ---
75
include/tcg/tcg-opc.h | 28 +--
76
include/tcg/tcg.h | 3 +-
77
linux-user/aarch64/target_signal.h | 2 +
78
linux-user/arm/target_signal.h | 2 +
79
linux-user/generic/signal.h | 1 -
80
linux-user/i386/target_signal.h | 2 +
81
linux-user/m68k/target_signal.h | 1 +
82
linux-user/microblaze/target_signal.h | 2 +
83
linux-user/ppc/target_signal.h | 2 +
84
linux-user/s390x/target_signal.h | 2 +
85
linux-user/sh4/target_signal.h | 2 +
86
linux-user/x86_64/target_signal.h | 2 +
87
linux-user/xtensa/target_signal.h | 2 +
88
tcg/aarch64/tcg-target-con-set.h | 12 +-
89
tcg/aarch64/tcg-target.h | 2 +
90
tcg/loongarch64/tcg-target-con-set.h | 15 +-
91
tcg/loongarch64/tcg-target-con-str.h | 1 -
92
tcg/loongarch64/tcg-target-has.h | 2 -
93
tcg/loongarch64/tcg-target.h | 2 +
94
tcg/mips/tcg-target-con-set.h | 26 +--
95
tcg/mips/tcg-target-con-str.h | 1 -
96
tcg/mips/tcg-target.h | 2 +
97
tcg/riscv/tcg-target-con-set.h | 10 +-
98
tcg/riscv/tcg-target-con-str.h | 1 -
99
tcg/riscv/tcg-target-has.h | 2 -
100
tcg/riscv/tcg-target.h | 2 +
101
tcg/sparc64/tcg-target-con-set.h | 12 +-
102
tcg/sparc64/tcg-target-con-str.h | 1 -
103
tcg/sparc64/tcg-target.h | 3 +-
104
tcg/tci/tcg-target.h | 1 -
105
accel/tcg/cputlb.c | 32 +---
106
accel/tcg/tcg-all.c | 9 +-
107
linux-user/elfload.c | 4 +-
108
plugins/api.c | 2 +-
109
target/arm/ptw.c | 34 ----
110
target/loongarch/tcg/translate.c | 2 +-
111
target/riscv/cpu_helper.c | 13 +-
112
target/sparc/gdbstub.c | 18 +-
113
target/sparc/translate.c | 19 +++
114
tcg/optimize.c | 21 +--
115
tcg/tcg-op-ldst.c | 103 +++--------
116
tcg/tcg.c | 97 +++++------
117
tcg/tci.c | 119 +++----------
118
docs/devel/multi-thread-tcg.rst | 1 -
119
docs/devel/tcg-ops.rst | 4 +-
120
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
121
target/sparc/insns.decode | 19 ++-
122
tcg/aarch64/tcg-target.c.inc | 86 ++++------
123
tcg/arm/tcg-target.c.inc | 114 ++++---------
124
tcg/i386/tcg-target.c.inc | 190 +++++----------------
125
tcg/loongarch64/tcg-target.c.inc | 72 +++-----
126
tcg/mips/tcg-target.c.inc | 169 ++++++------------
127
tcg/ppc/tcg-target.c.inc | 164 +++++-------------
128
tcg/riscv/tcg-target.c.inc | 56 +++---
129
tcg/s390x/tcg-target.c.inc | 40 ++---
130
tcg/sparc64/tcg-target.c.inc | 45 ++---
131
tcg/tci/tcg-target.c.inc | 60 ++-----
132
61 files changed, 548 insertions(+), 1160 deletions(-)
133
delete mode 100644 include/tcg/oversized-guest.h
diff view generated by jsdifflib
New patch
[PULL 01/23] linux-user/main: Allow setting tb-size
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
1
2
3
While qemu-system can set tb-size using -accel tcg,tb-size=n, there
4
is no similar knob for qemu-user. Add one in a way similar to how
5
one-insn-per-tb is already handled.
6
7
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-ID: <20240730215532.1442-1-iii@linux.ibm.com>
11
---
12
linux-user/main.c | 12 ++++++++++++
13
1 file changed, 12 insertions(+)
14
15
diff --git a/linux-user/main.c b/linux-user/main.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/linux-user/main.c
18
+++ b/linux-user/main.c
19
@@ -XXX,XX +XXX,XX @@ char *exec_path;
20
char real_exec_path[PATH_MAX];
21
22
static bool opt_one_insn_per_tb;
23
+static unsigned long opt_tb_size;
24
static const char *argv0;
25
static const char *gdbstub;
26
static envlist_t *envlist;
27
@@ -XXX,XX +XXX,XX @@ static void handle_arg_one_insn_per_tb(const char *arg)
28
opt_one_insn_per_tb = true;
29
}
30
31
+static void handle_arg_tb_size(const char *arg)
32
+{
33
+ if (qemu_strtoul(arg, NULL, 0, &opt_tb_size)) {
34
+ usage(EXIT_FAILURE);
35
+ }
36
+}
37
+
38
static void handle_arg_strace(const char *arg)
39
{
40
enable_strace = true;
41
@@ -XXX,XX +XXX,XX @@ static const struct qemu_argument arg_table[] = {
42
{"one-insn-per-tb",
43
"QEMU_ONE_INSN_PER_TB", false, handle_arg_one_insn_per_tb,
44
"", "run with one guest instruction per emulated TB"},
45
+ {"tb-size", "QEMU_TB_SIZE", true, handle_arg_tb_size,
46
+ "size", "TCG translation block cache size"},
47
{"strace", "QEMU_STRACE", false, handle_arg_strace,
48
"", "log system calls"},
49
{"seed", "QEMU_RAND_SEED", true, handle_arg_seed,
50
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv, char **envp)
51
accel_init_interfaces(ac);
52
object_property_set_bool(OBJECT(accel), "one-insn-per-tb",
53
opt_one_insn_per_tb, &error_abort);
54
+ object_property_set_int(OBJECT(accel), "tb-size",
55
+ opt_tb_size, &error_abort);
56
ac->init_machine(NULL);
57
}
58
59
--
60
2.43.0
61
62
diff view generated by jsdifflib
New patch
[PULL 02/23] accel/tcg: Restrict CPU_TLB_DYN_*_BITS definitions to accel/tcg/
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
CPU_TLB_DYN_*_BITS definitions are only used by accel/tcg/cputlb.c
4
and accel/tcg/translate-all.c. Move them to accel/tcg/tb-internal.h.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-ID: <20250305191859.71608-1-philmd@linaro.org>
10
---
11
accel/tcg/tb-internal.h | 27 +++++++++++++++++++++++++++
12
include/exec/cpu-defs.h | 26 --------------------------
13
2 files changed, 27 insertions(+), 26 deletions(-)
14
15
diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/accel/tcg/tb-internal.h
18
+++ b/accel/tcg/tb-internal.h
19
@@ -XXX,XX +XXX,XX @@
20
#include "exec/exec-all.h"
21
#include "exec/translation-block.h"
22
23
+#ifdef CONFIG_SOFTMMU
24
+
25
+#define CPU_TLB_DYN_MIN_BITS 6
26
+#define CPU_TLB_DYN_DEFAULT_BITS 8
27
+
28
+# if HOST_LONG_BITS == 32
29
+/* Make sure we do not require a double-word shift for the TLB load */
30
+# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS)
31
+# else /* HOST_LONG_BITS == 64 */
32
+/*
33
+ * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) ==
34
+ * 2**34 == 16G of address space. This is roughly what one would expect a
35
+ * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel
36
+ * Skylake's Level-2 STLB has 16 1G entries.
37
+ * Also, make sure we do not size the TLB past the guest's address space.
38
+ */
39
+# ifdef TARGET_PAGE_BITS_VARY
40
+# define CPU_TLB_DYN_MAX_BITS \
41
+ MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
42
+# else
43
+# define CPU_TLB_DYN_MAX_BITS \
44
+ MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
45
+# endif
46
+# endif
47
+
48
+#endif /* CONFIG_SOFTMMU */
49
+
50
#ifdef CONFIG_USER_ONLY
51
#include "user/page-protection.h"
52
/*
53
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
54
index XXXXXXX..XXXXXXX 100644
55
--- a/include/exec/cpu-defs.h
56
+++ b/include/exec/cpu-defs.h
57
@@ -XXX,XX +XXX,XX @@
58
59
#include "exec/target_long.h"
60
61
-#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
62
-#define CPU_TLB_DYN_MIN_BITS 6
63
-#define CPU_TLB_DYN_DEFAULT_BITS 8
64
-
65
-# if HOST_LONG_BITS == 32
66
-/* Make sure we do not require a double-word shift for the TLB load */
67
-# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS)
68
-# else /* HOST_LONG_BITS == 64 */
69
-/*
70
- * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) ==
71
- * 2**34 == 16G of address space. This is roughly what one would expect a
72
- * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel
73
- * Skylake's Level-2 STLB has 16 1G entries.
74
- * Also, make sure we do not size the TLB past the guest's address space.
75
- */
76
-# ifdef TARGET_PAGE_BITS_VARY
77
-# define CPU_TLB_DYN_MAX_BITS \
78
- MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
79
-# else
80
-# define CPU_TLB_DYN_MAX_BITS \
81
- MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
82
-# endif
83
-# endif
84
-
85
-#endif /* CONFIG_SOFTMMU && CONFIG_TCG */
86
-
87
#endif
88
--
89
2.43.0
90
91
diff view generated by jsdifflib
New patch
[PULL 03/23] include/exec: Move TARGET_PAGE_{SIZE, MASK, BITS} to target_page.h
1
Re-use the TARGET_PAGE_BITS_VARY mechanism to define
2
TARGET_PAGE_SIZE and friends when not compiling per-target.
3
Inline qemu_target_page_{size,mask,bits} as they are now trivial.
1
4
5
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
include/exec/cpu-all.h | 21 +-------------
9
include/exec/poison.h | 4 ---
10
include/exec/target_page.h | 58 ++++++++++++++++++++++++++++++++++----
11
page-target.c | 18 ------------
12
page-vary-target.c | 2 --
13
5 files changed, 53 insertions(+), 50 deletions(-)
14
15
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/exec/cpu-all.h
18
+++ b/include/exec/cpu-all.h
19
@@ -XXX,XX +XXX,XX @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val
20
21
/* page related stuff */
22
#include "exec/cpu-defs.h"
23
-#ifdef TARGET_PAGE_BITS_VARY
24
-# include "exec/page-vary.h"
25
-extern const TargetPageBits target_page;
26
-# ifdef CONFIG_DEBUG_TCG
27
-# define TARGET_PAGE_BITS ({ assert(target_page.decided); \
28
- target_page.bits; })
29
-# define TARGET_PAGE_MASK ({ assert(target_page.decided); \
30
- (target_long)target_page.mask; })
31
-# else
32
-# define TARGET_PAGE_BITS target_page.bits
33
-# define TARGET_PAGE_MASK ((target_long)target_page.mask)
34
-# endif
35
-# define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
36
-#else
37
-# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
38
-# define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
39
-# define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
40
-#endif
41
-
42
-#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
43
+#include "exec/target_page.h"
44
45
CPUArchState *cpu_copy(CPUArchState *env);
46
47
diff --git a/include/exec/poison.h b/include/exec/poison.h
48
index XXXXXXX..XXXXXXX 100644
49
--- a/include/exec/poison.h
50
+++ b/include/exec/poison.h
51
@@ -XXX,XX +XXX,XX @@
52
#pragma GCC poison TARGET_FMT_ld
53
#pragma GCC poison TARGET_FMT_lu
54
55
-#pragma GCC poison TARGET_PAGE_SIZE
56
-#pragma GCC poison TARGET_PAGE_MASK
57
-#pragma GCC poison TARGET_PAGE_BITS
58
-#pragma GCC poison TARGET_PAGE_ALIGN
59
#pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS
60
61
#pragma GCC poison CPU_INTERRUPT_HARD
62
diff --git a/include/exec/target_page.h b/include/exec/target_page.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/include/exec/target_page.h
65
+++ b/include/exec/target_page.h
66
@@ -XXX,XX +XXX,XX @@
67
#ifndef EXEC_TARGET_PAGE_H
68
#define EXEC_TARGET_PAGE_H
69
70
-size_t qemu_target_page_size(void);
71
-int qemu_target_page_mask(void);
72
-int qemu_target_page_bits(void);
73
-int qemu_target_page_bits_min(void);
74
-
75
-size_t qemu_target_pages_to_MiB(size_t pages);
76
+/*
77
+ * If compiling per-target, get the real values.
78
+ * For generic code, reuse the mechanism for variable page size.
79
+ */
80
+#ifdef COMPILING_PER_TARGET
81
+#include "cpu-param.h"
82
+#include "exec/target_long.h"
83
+#define TARGET_PAGE_TYPE target_long
84
+#else
85
+#define TARGET_PAGE_BITS_VARY
86
+#define TARGET_PAGE_TYPE int
87
+#endif
88
+
89
+#ifdef TARGET_PAGE_BITS_VARY
90
+# include "exec/page-vary.h"
91
+extern const TargetPageBits target_page;
92
+# ifdef CONFIG_DEBUG_TCG
93
+# define TARGET_PAGE_BITS ({ assert(target_page.decided); \
94
+ target_page.bits; })
95
+# define TARGET_PAGE_MASK ({ assert(target_page.decided); \
96
+ (TARGET_PAGE_TYPE)target_page.mask; })
97
+# else
98
+# define TARGET_PAGE_BITS target_page.bits
99
+# define TARGET_PAGE_MASK ((TARGET_PAGE_TYPE)target_page.mask)
100
+# endif
101
+# define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
102
+#else
103
+# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
104
+# define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
105
+# define TARGET_PAGE_MASK ((TARGET_PAGE_TYPE)-1 << TARGET_PAGE_BITS)
106
+#endif
107
+
108
+#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
109
+
110
+static inline size_t qemu_target_page_size(void)
111
+{
112
+ return TARGET_PAGE_SIZE;
113
+}
114
+
115
+static inline int qemu_target_page_mask(void)
116
+{
117
+ return TARGET_PAGE_MASK;
118
+}
119
+
120
+static inline int qemu_target_page_bits(void)
121
+{
122
+ return TARGET_PAGE_BITS;
123
+}
124
+
125
+int qemu_target_page_bits_min(void);
126
+size_t qemu_target_pages_to_MiB(size_t pages);
127
+
128
#endif
129
diff --git a/page-target.c b/page-target.c
130
index XXXXXXX..XXXXXXX 100644
131
--- a/page-target.c
132
+++ b/page-target.c
133
@@ -XXX,XX +XXX,XX @@
134
135
#include "qemu/osdep.h"
136
#include "exec/target_page.h"
137
-#include "exec/cpu-defs.h"
138
-#include "cpu.h"
139
-#include "exec/cpu-all.h"
140
-
141
-size_t qemu_target_page_size(void)
142
-{
143
- return TARGET_PAGE_SIZE;
144
-}
145
-
146
-int qemu_target_page_mask(void)
147
-{
148
- return TARGET_PAGE_MASK;
149
-}
150
-
151
-int qemu_target_page_bits(void)
152
-{
153
- return TARGET_PAGE_BITS;
154
-}
155
156
int qemu_target_page_bits_min(void)
157
{
158
diff --git a/page-vary-target.c b/page-vary-target.c
159
index XXXXXXX..XXXXXXX 100644
160
--- a/page-vary-target.c
161
+++ b/page-vary-target.c
162
@@ -XXX,XX +XXX,XX @@ bool set_preferred_target_page_bits(int bits)
163
164
void finalize_target_page_bits(void)
165
{
166
-#ifdef TARGET_PAGE_BITS_VARY
167
finalize_target_page_bits_common(TARGET_PAGE_BITS_MIN);
168
-#endif
169
}
170
--
171
2.43.0
diff view generated by jsdifflib
New patch
[PULL 04/23] include/exec: Split out exec/cpu-interrupt.h
1
Some of these bits are actually common to all cpus; while the
2
reset have common reservations for target-specific usage.
3
While generic code cannot know what the target-specific usage is,
4
common code can know what to do with the bits, e.g. single-step.
1
5
6
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
include/exec/cpu-all.h | 53 +--------------------------
12
include/exec/cpu-interrupt.h | 70 ++++++++++++++++++++++++++++++++++++
13
include/exec/poison.h | 13 -------
14
3 files changed, 71 insertions(+), 65 deletions(-)
15
create mode 100644 include/exec/cpu-interrupt.h
16
17
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/exec/cpu-all.h
20
+++ b/include/exec/cpu-all.h
21
@@ -XXX,XX +XXX,XX @@
22
23
#include "exec/page-protection.h"
24
#include "exec/cpu-common.h"
25
+#include "exec/cpu-interrupt.h"
26
#include "exec/memory.h"
27
#include "exec/tswap.h"
28
#include "hw/core/cpu.h"
29
@@ -XXX,XX +XXX,XX @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val
30
31
CPUArchState *cpu_copy(CPUArchState *env);
32
33
-/* Flags for use in ENV->INTERRUPT_PENDING.
34
-
35
- The numbers assigned here are non-sequential in order to preserve
36
- binary compatibility with the vmstate dump. Bit 0 (0x0001) was
37
- previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
38
- the vmstate dump. */
39
-
40
-/* External hardware interrupt pending. This is typically used for
41
- interrupts from devices. */
42
-#define CPU_INTERRUPT_HARD 0x0002
43
-
44
-/* Exit the current TB. This is typically used when some system-level device
45
- makes some change to the memory mapping. E.g. the a20 line change. */
46
-#define CPU_INTERRUPT_EXITTB 0x0004
47
-
48
-/* Halt the CPU. */
49
-#define CPU_INTERRUPT_HALT 0x0020
50
-
51
-/* Debug event pending. */
52
-#define CPU_INTERRUPT_DEBUG 0x0080
53
-
54
-/* Reset signal. */
55
-#define CPU_INTERRUPT_RESET 0x0400
56
-
57
-/* Several target-specific external hardware interrupts. Each target/cpu.h
58
- should define proper names based on these defines. */
59
-#define CPU_INTERRUPT_TGT_EXT_0 0x0008
60
-#define CPU_INTERRUPT_TGT_EXT_1 0x0010
61
-#define CPU_INTERRUPT_TGT_EXT_2 0x0040
62
-#define CPU_INTERRUPT_TGT_EXT_3 0x0200
63
-#define CPU_INTERRUPT_TGT_EXT_4 0x1000
64
-
65
-/* Several target-specific internal interrupts. These differ from the
66
- preceding target-specific interrupts in that they are intended to
67
- originate from within the cpu itself, typically in response to some
68
- instruction being executed. These, therefore, are not masked while
69
- single-stepping within the debugger. */
70
-#define CPU_INTERRUPT_TGT_INT_0 0x0100
71
-#define CPU_INTERRUPT_TGT_INT_1 0x0800
72
-#define CPU_INTERRUPT_TGT_INT_2 0x2000
73
-
74
-/* First unused bit: 0x4000. */
75
-
76
-/* The set of all bits that should be masked when single-stepping. */
77
-#define CPU_INTERRUPT_SSTEP_MASK \
78
- (CPU_INTERRUPT_HARD \
79
- | CPU_INTERRUPT_TGT_EXT_0 \
80
- | CPU_INTERRUPT_TGT_EXT_1 \
81
- | CPU_INTERRUPT_TGT_EXT_2 \
82
- | CPU_INTERRUPT_TGT_EXT_3 \
83
- | CPU_INTERRUPT_TGT_EXT_4)
84
-
85
#include "cpu.h"
86
87
#ifdef CONFIG_USER_ONLY
88
diff --git a/include/exec/cpu-interrupt.h b/include/exec/cpu-interrupt.h
89
new file mode 100644
90
index XXXXXXX..XXXXXXX
91
--- /dev/null
92
+++ b/include/exec/cpu-interrupt.h
93
@@ -XXX,XX +XXX,XX @@
94
+/*
95
+ * Flags for use with cpu_interrupt()
96
+ *
97
+ * Copyright (c) 2003 Fabrice Bellard
98
+ * SPDX-License-Identifier: LGPL-2.1-or-later
99
+ */
100
+
101
+#ifndef CPU_INTERRUPT_H
102
+#define CPU_INTERRUPT_H
103
+
104
+/*
105
+ * The numbers assigned here are non-sequential in order to preserve binary
106
+ * compatibility with the vmstate dump. Bit 0 (0x0001) was previously used
107
+ * for CPU_INTERRUPT_EXIT, and is cleared when loading the vmstate dump.
108
+ */
109
+
110
+/*
111
+ * External hardware interrupt pending.
112
+ * This is typically used for interrupts from devices.
113
+ */
114
+#define CPU_INTERRUPT_HARD 0x0002
115
+
116
+/*
117
+ * Exit the current TB. This is typically used when some system-level device
118
+ * makes some change to the memory mapping. E.g. the a20 line change.
119
+ */
120
+#define CPU_INTERRUPT_EXITTB 0x0004
121
+
122
+/* Halt the CPU. */
123
+#define CPU_INTERRUPT_HALT 0x0020
124
+
125
+/* Debug event pending. */
126
+#define CPU_INTERRUPT_DEBUG 0x0080
127
+
128
+/* Reset signal. */
129
+#define CPU_INTERRUPT_RESET 0x0400
130
+
131
+/*
132
+ * Several target-specific external hardware interrupts. Each target/cpu.h
133
+ * should define proper names based on these defines.
134
+ */
135
+#define CPU_INTERRUPT_TGT_EXT_0 0x0008
136
+#define CPU_INTERRUPT_TGT_EXT_1 0x0010
137
+#define CPU_INTERRUPT_TGT_EXT_2 0x0040
138
+#define CPU_INTERRUPT_TGT_EXT_3 0x0200
139
+#define CPU_INTERRUPT_TGT_EXT_4 0x1000
140
+
141
+/*
142
+ * Several target-specific internal interrupts. These differ from the
143
+ * preceding target-specific interrupts in that they are intended to
144
+ * originate from within the cpu itself, typically in response to some
145
+ * instruction being executed. These, therefore, are not masked while
146
+ * single-stepping within the debugger.
147
+ */
148
+#define CPU_INTERRUPT_TGT_INT_0 0x0100
149
+#define CPU_INTERRUPT_TGT_INT_1 0x0800
150
+#define CPU_INTERRUPT_TGT_INT_2 0x2000
151
+
152
+/* First unused bit: 0x4000. */
153
+
154
+/* The set of all bits that should be masked when single-stepping. */
155
+#define CPU_INTERRUPT_SSTEP_MASK \
156
+ (CPU_INTERRUPT_HARD \
157
+ | CPU_INTERRUPT_TGT_EXT_0 \
158
+ | CPU_INTERRUPT_TGT_EXT_1 \
159
+ | CPU_INTERRUPT_TGT_EXT_2 \
160
+ | CPU_INTERRUPT_TGT_EXT_3 \
161
+ | CPU_INTERRUPT_TGT_EXT_4)
162
+
163
+#endif /* CPU_INTERRUPT_H */
164
diff --git a/include/exec/poison.h b/include/exec/poison.h
165
index XXXXXXX..XXXXXXX 100644
166
--- a/include/exec/poison.h
167
+++ b/include/exec/poison.h
168
@@ -XXX,XX +XXX,XX @@
169
170
#pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS
171
172
-#pragma GCC poison CPU_INTERRUPT_HARD
173
-#pragma GCC poison CPU_INTERRUPT_EXITTB
174
-#pragma GCC poison CPU_INTERRUPT_HALT
175
-#pragma GCC poison CPU_INTERRUPT_DEBUG
176
-#pragma GCC poison CPU_INTERRUPT_TGT_EXT_0
177
-#pragma GCC poison CPU_INTERRUPT_TGT_EXT_1
178
-#pragma GCC poison CPU_INTERRUPT_TGT_EXT_2
179
-#pragma GCC poison CPU_INTERRUPT_TGT_EXT_3
180
-#pragma GCC poison CPU_INTERRUPT_TGT_EXT_4
181
-#pragma GCC poison CPU_INTERRUPT_TGT_INT_0
182
-#pragma GCC poison CPU_INTERRUPT_TGT_INT_1
183
-#pragma GCC poison CPU_INTERRUPT_TGT_INT_2
184
-
185
#pragma GCC poison CONFIG_ALPHA_DIS
186
#pragma GCC poison CONFIG_HPPA_DIS
187
#pragma GCC poison CONFIG_I386_DIS
188
--
189
2.43.0
190
191
diff view generated by jsdifflib
New patch
[PULL 05/23] accel/tcg: Compile watchpoint.c once
1
Move tb_check_watchpoint declaration from tb-internal.h, which is
2
still target-specific, to internal-common.h, which isn't.
3
Otherwise, all that is required to build watchpoint.c once is
4
to include the new exec/cpu-interrupt.h instead of exec/exec-all.h.
1
5
6
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
accel/tcg/internal-common.h | 2 ++
12
accel/tcg/tb-internal.h | 2 --
13
accel/tcg/watchpoint.c | 5 ++---
14
accel/tcg/meson.build | 2 +-
15
4 files changed, 5 insertions(+), 6 deletions(-)
16
17
diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/accel/tcg/internal-common.h
20
+++ b/accel/tcg/internal-common.h
21
@@ -XXX,XX +XXX,XX @@ void tcg_exec_unrealizefn(CPUState *cpu);
22
/* current cflags for hashing/comparison */
23
uint32_t curr_cflags(CPUState *cpu);
24
25
+void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr);
26
+
27
#endif
28
diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/accel/tcg/tb-internal.h
31
+++ b/accel/tcg/tb-internal.h
32
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_range_fast(ram_addr_t ram_addr,
33
34
bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc);
35
36
-void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr);
37
-
38
#endif
39
diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/accel/tcg/watchpoint.c
42
+++ b/accel/tcg/watchpoint.c
43
@@ -XXX,XX +XXX,XX @@
44
45
#include "qemu/osdep.h"
46
#include "qemu/main-loop.h"
47
-#include "qemu/error-report.h"
48
-#include "exec/exec-all.h"
49
+#include "exec/breakpoint.h"
50
+#include "exec/cpu-interrupt.h"
51
#include "exec/page-protection.h"
52
#include "exec/translation-block.h"
53
-#include "tb-internal.h"
54
#include "system/tcg.h"
55
#include "system/replay.h"
56
#include "accel/tcg/cpu-ops.h"
57
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
58
index XXXXXXX..XXXXXXX 100644
59
--- a/accel/tcg/meson.build
60
+++ b/accel/tcg/meson.build
61
@@ -XXX,XX +XXX,XX @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
62
63
specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
64
'cputlb.c',
65
- 'watchpoint.c',
66
'tcg-accel-ops.c',
67
'tcg-accel-ops-mttcg.c',
68
'tcg-accel-ops-icount.c',
69
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
70
system_ss.add(when: ['CONFIG_TCG'], if_true: files(
71
'icount-common.c',
72
'monitor.c',
73
+ 'watchpoint.c',
74
))
75
--
76
2.43.0
77
78
diff view generated by jsdifflib
New patch
[PULL 06/23] exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h'
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Move CPU TLB related methods to "exec/cputlb.h".
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Message-ID: <20241114011310.3615-14-philmd@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
10
include/exec/cputlb.h | 7 +++++++
11
include/exec/exec-all.h | 3 ---
12
include/exec/ram_addr.h | 1 +
13
system/physmem.c | 1 +
14
4 files changed, 9 insertions(+), 3 deletions(-)
15
16
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/exec/cputlb.h
19
+++ b/include/exec/cputlb.h
20
@@ -XXX,XX +XXX,XX @@ void tlb_unprotect_code(ram_addr_t ram_addr);
21
22
#endif /* CONFIG_TCG */
23
24
+#ifndef CONFIG_USER_ONLY
25
+
26
+void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
27
+void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
28
+
29
+#endif
30
+
31
#endif
32
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/include/exec/exec-all.h
35
+++ b/include/exec/exec-all.h
36
@@ -XXX,XX +XXX,XX @@ static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
37
38
#if !defined(CONFIG_USER_ONLY)
39
40
-void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
41
-void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
42
-
43
MemoryRegionSection *
44
address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
45
hwaddr *xlat, hwaddr *plen,
46
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/include/exec/ram_addr.h
49
+++ b/include/exec/ram_addr.h
50
@@ -XXX,XX +XXX,XX @@
51
#include "cpu.h"
52
#include "system/xen.h"
53
#include "system/tcg.h"
54
+#include "exec/cputlb.h"
55
#include "exec/ramlist.h"
56
#include "exec/ramblock.h"
57
#include "exec/exec-all.h"
58
diff --git a/system/physmem.c b/system/physmem.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/system/physmem.c
61
+++ b/system/physmem.c
62
@@ -XXX,XX +XXX,XX @@
63
#endif /* CONFIG_TCG */
64
65
#include "exec/exec-all.h"
66
+#include "exec/cputlb.h"
67
#include "exec/page-protection.h"
68
#include "exec/target_page.h"
69
#include "exec/translation-block.h"
70
--
71
2.43.0
72
73
diff view generated by jsdifflib
New patch
[PULL 07/23] exec: Declare tlb_set_page_full() in 'exec/cputlb.h'
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Move CPU TLB related methods to "exec/cputlb.h".
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-ID: <20241114011310.3615-16-philmd@linaro.org>
9
---
10
include/exec/cputlb.h | 23 +++++++++++++++++++++++
11
include/exec/exec-all.h | 22 ----------------------
12
target/sparc/mmu_helper.c | 2 +-
13
3 files changed, 24 insertions(+), 23 deletions(-)
14
15
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/exec/cputlb.h
18
+++ b/include/exec/cputlb.h
19
@@ -XXX,XX +XXX,XX @@
20
#define CPUTLB_H
21
22
#include "exec/cpu-common.h"
23
+#include "exec/vaddr.h"
24
25
#ifdef CONFIG_TCG
26
27
@@ -XXX,XX +XXX,XX @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
28
29
#endif
30
31
+/**
32
+ * tlb_set_page_full:
33
+ * @cpu: CPU context
34
+ * @mmu_idx: mmu index of the tlb to modify
35
+ * @addr: virtual address of the entry to add
36
+ * @full: the details of the tlb entry
37
+ *
38
+ * Add an entry to @cpu tlb index @mmu_idx. All of the fields of
39
+ * @full must be filled, except for xlat_section, and constitute
40
+ * the complete description of the translated page.
41
+ *
42
+ * This is generally called by the target tlb_fill function after
43
+ * having performed a successful page table walk to find the physical
44
+ * address and attributes for the translation.
45
+ *
46
+ * At most one entry for a given virtual address is permitted. Only a
47
+ * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
48
+ * used by tlb_flush_page.
49
+ */
50
+void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,
51
+ CPUTLBEntryFull *full);
52
+
53
#endif
54
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
55
index XXXXXXX..XXXXXXX 100644
56
--- a/include/exec/exec-all.h
57
+++ b/include/exec/exec-all.h
58
@@ -XXX,XX +XXX,XX @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
59
uint16_t idxmap,
60
unsigned bits);
61
62
-/**
63
- * tlb_set_page_full:
64
- * @cpu: CPU context
65
- * @mmu_idx: mmu index of the tlb to modify
66
- * @addr: virtual address of the entry to add
67
- * @full: the details of the tlb entry
68
- *
69
- * Add an entry to @cpu tlb index @mmu_idx. All of the fields of
70
- * @full must be filled, except for xlat_section, and constitute
71
- * the complete description of the translated page.
72
- *
73
- * This is generally called by the target tlb_fill function after
74
- * having performed a successful page table walk to find the physical
75
- * address and attributes for the translation.
76
- *
77
- * At most one entry for a given virtual address is permitted. Only a
78
- * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
79
- * used by tlb_flush_page.
80
- */
81
-void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,
82
- CPUTLBEntryFull *full);
83
-
84
/**
85
* tlb_set_page_with_attrs:
86
* @cpu: CPU to add this TLB entry for
87
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/target/sparc/mmu_helper.c
90
+++ b/target/sparc/mmu_helper.c
91
@@ -XXX,XX +XXX,XX @@
92
#include "qemu/osdep.h"
93
#include "qemu/log.h"
94
#include "cpu.h"
95
-#include "exec/exec-all.h"
96
+#include "exec/cputlb.h"
97
#include "exec/page-protection.h"
98
#include "qemu/qemu-print.h"
99
#include "trace.h"
100
--
101
2.43.0
102
103
diff view generated by jsdifflib
New patch
[PULL 08/23] exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h'
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Move CPU TLB related methods to "exec/cputlb.h".
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-ID: <20241114011310.3615-17-philmd@linaro.org>
9
---
10
include/exec/cputlb.h | 28 ++++++++++++++++++++++++++++
11
include/exec/exec-all.h | 25 -------------------------
12
target/i386/tcg/system/excp_helper.c | 2 +-
13
target/microblaze/helper.c | 2 +-
14
4 files changed, 30 insertions(+), 27 deletions(-)
15
16
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/exec/cputlb.h
19
+++ b/include/exec/cputlb.h
20
@@ -XXX,XX +XXX,XX @@
21
#define CPUTLB_H
22
23
#include "exec/cpu-common.h"
24
+#include "exec/hwaddr.h"
25
+#include "exec/memattrs.h"
26
#include "exec/vaddr.h"
27
28
#ifdef CONFIG_TCG
29
@@ -XXX,XX +XXX,XX @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
30
void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,
31
CPUTLBEntryFull *full);
32
33
+/**
34
+ * tlb_set_page_with_attrs:
35
+ * @cpu: CPU to add this TLB entry for
36
+ * @addr: virtual address of page to add entry for
37
+ * @paddr: physical address of the page
38
+ * @attrs: memory transaction attributes
39
+ * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
40
+ * @mmu_idx: MMU index to insert TLB entry for
41
+ * @size: size of the page in bytes
42
+ *
43
+ * Add an entry to this CPU's TLB (a mapping from virtual address
44
+ * @addr to physical address @paddr) with the specified memory
45
+ * transaction attributes. This is generally called by the target CPU
46
+ * specific code after it has been called through the tlb_fill()
47
+ * entry point and performed a successful page table walk to find
48
+ * the physical address and attributes for the virtual address
49
+ * which provoked the TLB miss.
50
+ *
51
+ * At most one entry for a given virtual address is permitted. Only a
52
+ * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
53
+ * used by tlb_flush_page.
54
+ */
55
+void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
56
+ hwaddr paddr, MemTxAttrs attrs,
57
+ int prot, int mmu_idx, vaddr size);
58
+
59
#endif
60
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
61
index XXXXXXX..XXXXXXX 100644
62
--- a/include/exec/exec-all.h
63
+++ b/include/exec/exec-all.h
64
@@ -XXX,XX +XXX,XX @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
65
uint16_t idxmap,
66
unsigned bits);
67
68
-/**
69
- * tlb_set_page_with_attrs:
70
- * @cpu: CPU to add this TLB entry for
71
- * @addr: virtual address of page to add entry for
72
- * @paddr: physical address of the page
73
- * @attrs: memory transaction attributes
74
- * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
75
- * @mmu_idx: MMU index to insert TLB entry for
76
- * @size: size of the page in bytes
77
- *
78
- * Add an entry to this CPU's TLB (a mapping from virtual address
79
- * @addr to physical address @paddr) with the specified memory
80
- * transaction attributes. This is generally called by the target CPU
81
- * specific code after it has been called through the tlb_fill()
82
- * entry point and performed a successful page table walk to find
83
- * the physical address and attributes for the virtual address
84
- * which provoked the TLB miss.
85
- *
86
- * At most one entry for a given virtual address is permitted. Only a
87
- * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
88
- * used by tlb_flush_page.
89
- */
90
-void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
91
- hwaddr paddr, MemTxAttrs attrs,
92
- int prot, int mmu_idx, vaddr size);
93
/* tlb_set_page:
94
*
95
* This function is equivalent to calling tlb_set_page_with_attrs()
96
diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/excp_helper.c
97
index XXXXXXX..XXXXXXX 100644
98
--- a/target/i386/tcg/system/excp_helper.c
99
+++ b/target/i386/tcg/system/excp_helper.c
100
@@ -XXX,XX +XXX,XX @@
101
#include "qemu/osdep.h"
102
#include "cpu.h"
103
#include "exec/cpu_ldst.h"
104
-#include "exec/exec-all.h"
105
+#include "exec/cputlb.h"
106
#include "exec/page-protection.h"
107
#include "tcg/helper-tcg.h"
108
109
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
110
index XXXXXXX..XXXXXXX 100644
111
--- a/target/microblaze/helper.c
112
+++ b/target/microblaze/helper.c
113
@@ -XXX,XX +XXX,XX @@
114
115
#include "qemu/osdep.h"
116
#include "cpu.h"
117
-#include "exec/exec-all.h"
118
+#include "exec/cputlb.h"
119
#include "exec/page-protection.h"
120
#include "qemu/host-utils.h"
121
#include "exec/log.h"
122
--
123
2.43.0
124
125
diff view generated by jsdifflib
New patch
[PULL 09/23] exec: Declare tlb_set_page() in 'exec/cputlb.h'
1
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
3
Move CPU TLB related methods to "exec/cputlb.h".
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-ID: <20241114011310.3615-18-philmd@linaro.org>
9
---
10
include/exec/cputlb.h | 11 +++++++++++
11
include/exec/exec-all.h | 9 ---------
12
target/alpha/helper.c | 2 +-
13
target/avr/helper.c | 2 +-
14
target/loongarch/tcg/tlb_helper.c | 1 +
15
target/m68k/helper.c | 1 +
16
target/mips/tcg/system/tlb_helper.c | 1 +
17
target/openrisc/mmu.c | 2 +-
18
target/ppc/mmu_helper.c | 1 +
19
target/riscv/cpu_helper.c | 1 +
20
target/rx/cpu.c | 2 +-
21
target/s390x/tcg/excp_helper.c | 1 +
22
target/sh4/helper.c | 1 +
23
target/tricore/helper.c | 2 +-
24
target/xtensa/helper.c | 2 +-
25
15 files changed, 24 insertions(+), 15 deletions(-)
26
27
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/include/exec/cputlb.h
30
+++ b/include/exec/cputlb.h
31
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
32
hwaddr paddr, MemTxAttrs attrs,
33
int prot, int mmu_idx, vaddr size);
34
35
+/**
36
+ * tlb_set_page:
37
+ *
38
+ * This function is equivalent to calling tlb_set_page_with_attrs()
39
+ * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
40
+ * as a convenience for CPUs which don't use memory transaction attributes.
41
+ */
42
+void tlb_set_page(CPUState *cpu, vaddr addr,
43
+ hwaddr paddr, int prot,
44
+ int mmu_idx, vaddr size);
45
+
46
#endif
47
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
48
index XXXXXXX..XXXXXXX 100644
49
--- a/include/exec/exec-all.h
50
+++ b/include/exec/exec-all.h
51
@@ -XXX,XX +XXX,XX @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
52
uint16_t idxmap,
53
unsigned bits);
54
55
-/* tlb_set_page:
56
- *
57
- * This function is equivalent to calling tlb_set_page_with_attrs()
58
- * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
59
- * as a convenience for CPUs which don't use memory transaction attributes.
60
- */
61
-void tlb_set_page(CPUState *cpu, vaddr addr,
62
- hwaddr paddr, int prot,
63
- int mmu_idx, vaddr size);
64
#else
65
static inline void tlb_flush_page(CPUState *cpu, vaddr addr)
66
{
67
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/target/alpha/helper.c
70
+++ b/target/alpha/helper.c
71
@@ -XXX,XX +XXX,XX @@
72
#include "qemu/osdep.h"
73
#include "qemu/log.h"
74
#include "cpu.h"
75
-#include "exec/exec-all.h"
76
+#include "exec/cputlb.h"
77
#include "exec/page-protection.h"
78
#include "fpu/softfloat-types.h"
79
#include "exec/helper-proto.h"
80
diff --git a/target/avr/helper.c b/target/avr/helper.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/avr/helper.c
83
+++ b/target/avr/helper.c
84
@@ -XXX,XX +XXX,XX @@
85
#include "qemu/error-report.h"
86
#include "cpu.h"
87
#include "accel/tcg/cpu-ops.h"
88
-#include "exec/exec-all.h"
89
+#include "exec/cputlb.h"
90
#include "exec/page-protection.h"
91
#include "exec/cpu_ldst.h"
92
#include "exec/address-spaces.h"
93
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
94
index XXXXXXX..XXXXXXX 100644
95
--- a/target/loongarch/tcg/tlb_helper.c
96
+++ b/target/loongarch/tcg/tlb_helper.c
97
@@ -XXX,XX +XXX,XX @@
98
#include "cpu.h"
99
#include "internals.h"
100
#include "exec/helper-proto.h"
101
+#include "exec/cputlb.h"
102
#include "exec/exec-all.h"
103
#include "exec/page-protection.h"
104
#include "exec/cpu_ldst.h"
105
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
106
index XXXXXXX..XXXXXXX 100644
107
--- a/target/m68k/helper.c
108
+++ b/target/m68k/helper.c
109
@@ -XXX,XX +XXX,XX @@
110
111
#include "qemu/osdep.h"
112
#include "cpu.h"
113
+#include "exec/cputlb.h"
114
#include "exec/exec-all.h"
115
#include "exec/page-protection.h"
116
#include "exec/gdbstub.h"
117
diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/tlb_helper.c
118
index XXXXXXX..XXXXXXX 100644
119
--- a/target/mips/tcg/system/tlb_helper.c
120
+++ b/target/mips/tcg/system/tlb_helper.c
121
@@ -XXX,XX +XXX,XX @@
122
123
#include "cpu.h"
124
#include "internal.h"
125
+#include "exec/cputlb.h"
126
#include "exec/exec-all.h"
127
#include "exec/page-protection.h"
128
#include "exec/cpu_ldst.h"
129
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
130
index XXXXXXX..XXXXXXX 100644
131
--- a/target/openrisc/mmu.c
132
+++ b/target/openrisc/mmu.c
133
@@ -XXX,XX +XXX,XX @@
134
#include "qemu/osdep.h"
135
#include "qemu/log.h"
136
#include "cpu.h"
137
-#include "exec/exec-all.h"
138
+#include "exec/cputlb.h"
139
#include "exec/page-protection.h"
140
#include "gdbstub/helpers.h"
141
#include "qemu/host-utils.h"
142
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
143
index XXXXXXX..XXXXXXX 100644
144
--- a/target/ppc/mmu_helper.c
145
+++ b/target/ppc/mmu_helper.c
146
@@ -XXX,XX +XXX,XX @@
147
#include "kvm_ppc.h"
148
#include "mmu-hash64.h"
149
#include "mmu-hash32.h"
150
+#include "exec/cputlb.h"
151
#include "exec/exec-all.h"
152
#include "exec/page-protection.h"
153
#include "exec/log.h"
154
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
155
index XXXXXXX..XXXXXXX 100644
156
--- a/target/riscv/cpu_helper.c
157
+++ b/target/riscv/cpu_helper.c
158
@@ -XXX,XX +XXX,XX @@
159
#include "cpu.h"
160
#include "internals.h"
161
#include "pmu.h"
162
+#include "exec/cputlb.h"
163
#include "exec/exec-all.h"
164
#include "exec/page-protection.h"
165
#include "instmap.h"
166
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
167
index XXXXXXX..XXXXXXX 100644
168
--- a/target/rx/cpu.c
169
+++ b/target/rx/cpu.c
170
@@ -XXX,XX +XXX,XX @@
171
#include "qapi/error.h"
172
#include "cpu.h"
173
#include "migration/vmstate.h"
174
-#include "exec/exec-all.h"
175
+#include "exec/cputlb.h"
176
#include "exec/page-protection.h"
177
#include "exec/translation-block.h"
178
#include "hw/loader.h"
179
diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c
180
index XXXXXXX..XXXXXXX 100644
181
--- a/target/s390x/tcg/excp_helper.c
182
+++ b/target/s390x/tcg/excp_helper.c
183
@@ -XXX,XX +XXX,XX @@
184
#include "qemu/log.h"
185
#include "cpu.h"
186
#include "exec/helper-proto.h"
187
+#include "exec/cputlb.h"
188
#include "exec/exec-all.h"
189
#include "s390x-internal.h"
190
#include "tcg_s390x.h"
191
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
192
index XXXXXXX..XXXXXXX 100644
193
--- a/target/sh4/helper.c
194
+++ b/target/sh4/helper.c
195
@@ -XXX,XX +XXX,XX @@
196
#include "qemu/osdep.h"
197
198
#include "cpu.h"
199
+#include "exec/cputlb.h"
200
#include "exec/exec-all.h"
201
#include "exec/page-protection.h"
202
#include "exec/log.h"
203
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
204
index XXXXXXX..XXXXXXX 100644
205
--- a/target/tricore/helper.c
206
+++ b/target/tricore/helper.c
207
@@ -XXX,XX +XXX,XX @@
208
#include "qemu/log.h"
209
#include "hw/registerfields.h"
210
#include "cpu.h"
211
-#include "exec/exec-all.h"
212
+#include "exec/cputlb.h"
213
#include "exec/page-protection.h"
214
#include "fpu/softfloat-helpers.h"
215
#include "qemu/qemu-print.h"
216
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
217
index XXXXXXX..XXXXXXX 100644
218
--- a/target/xtensa/helper.c
219
+++ b/target/xtensa/helper.c
220
@@ -XXX,XX +XXX,XX @@
221
#include "qemu/osdep.h"
222
#include "qemu/log.h"
223
#include "cpu.h"
224
-#include "exec/exec-all.h"
225
+#include "exec/cputlb.h"
226
#include "gdbstub/helpers.h"
227
#include "exec/helper-proto.h"
228
#include "qemu/error-report.h"
229
--
230
2.43.0
231
232
diff view generated by jsdifflib
New patch
[PULL 10/23] exec: Declare tlb_hit*() in 'exec/cputlb.h'
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Move CPU TLB related methods to "exec/cputlb.h".
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-ID: <20241114011310.3615-20-philmd@linaro.org>
9
---
10
include/exec/cpu-all.h | 23 -----------------------
11
accel/tcg/cputlb.c | 23 +++++++++++++++++++++++
12
2 files changed, 23 insertions(+), 23 deletions(-)
13
14
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/exec/cpu-all.h
17
+++ b/include/exec/cpu-all.h
18
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
19
/* The two sets of flags must not overlap. */
20
QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK);
21
22
-/**
23
- * tlb_hit_page: return true if page aligned @addr is a hit against the
24
- * TLB entry @tlb_addr
25
- *
26
- * @addr: virtual address to test (must be page aligned)
27
- * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
28
- */
29
-static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr)
30
-{
31
- return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
32
-}
33
-
34
-/**
35
- * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
36
- *
37
- * @addr: virtual address to test (need not be page aligned)
38
- * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
39
- */
40
-static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr)
41
-{
42
- return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK);
43
-}
44
-
45
#endif /* !CONFIG_USER_ONLY */
46
47
/* Validate correct placement of CPUArchState. */
48
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/accel/tcg/cputlb.c
51
+++ b/accel/tcg/cputlb.c
52
@@ -XXX,XX +XXX,XX @@ void tlb_set_page(CPUState *cpu, vaddr addr,
53
prot, mmu_idx, size);
54
}
55
56
+/**
57
+ * tlb_hit_page: return true if page aligned @addr is a hit against the
58
+ * TLB entry @tlb_addr
59
+ *
60
+ * @addr: virtual address to test (must be page aligned)
61
+ * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
62
+ */
63
+static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr)
64
+{
65
+ return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
66
+}
67
+
68
+/**
69
+ * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
70
+ *
71
+ * @addr: virtual address to test (need not be page aligned)
72
+ * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
73
+ */
74
+static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr)
75
+{
76
+ return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK);
77
+}
78
+
79
/*
80
* Note: tlb_fill_align() can trigger a resize of the TLB.
81
* This means that all of the caller's prior references to the TLB table
82
--
83
2.43.0
84
85
diff view generated by jsdifflib
New patch
[PULL 11/23] exec: Declare tlb_flush*() in 'exec/cputlb.h'
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Move CPU TLB related methods to "exec/cputlb.h".
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
8
Message-ID: <20241114011310.3615-19-philmd@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
include/exec/cputlb.h | 200 +++++++++++++++++++++++++--
12
include/exec/exec-all.h | 184 ------------------------
13
accel/tcg/tcg-accel-ops.c | 2 +-
14
cpu-target.c | 1 +
15
hw/intc/armv7m_nvic.c | 2 +-
16
hw/ppc/spapr_nested.c | 1 +
17
hw/sh4/sh7750.c | 1 +
18
system/watchpoint.c | 3 +-
19
target/alpha/sys_helper.c | 2 +-
20
target/arm/helper.c | 1 +
21
target/arm/tcg/tlb-insns.c | 2 +-
22
target/hppa/mem_helper.c | 1 +
23
target/i386/helper.c | 2 +-
24
target/i386/machine.c | 2 +-
25
target/i386/tcg/fpu_helper.c | 2 +-
26
target/i386/tcg/misc_helper.c | 2 +-
27
target/i386/tcg/system/misc_helper.c | 2 +-
28
target/i386/tcg/system/svm_helper.c | 2 +-
29
target/loongarch/tcg/csr_helper.c | 2 +-
30
target/microblaze/mmu.c | 2 +-
31
target/mips/system/cp0.c | 2 +-
32
target/mips/tcg/system/cp0_helper.c | 2 +-
33
target/openrisc/sys_helper.c | 1 +
34
target/ppc/helper_regs.c | 2 +-
35
target/ppc/misc_helper.c | 1 +
36
target/riscv/csr.c | 1 +
37
target/riscv/op_helper.c | 1 +
38
target/riscv/pmp.c | 2 +-
39
target/s390x/gdbstub.c | 2 +-
40
target/s390x/sigp.c | 1 +
41
target/s390x/tcg/mem_helper.c | 1 +
42
target/s390x/tcg/misc_helper.c | 1 +
43
target/sparc/ldst_helper.c | 1 +
44
target/xtensa/mmu_helper.c | 1 +
45
34 files changed, 224 insertions(+), 211 deletions(-)
46
47
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
48
index XXXXXXX..XXXXXXX 100644
49
--- a/include/exec/cputlb.h
50
+++ b/include/exec/cputlb.h
51
@@ -XXX,XX +XXX,XX @@
52
#include "exec/memattrs.h"
53
#include "exec/vaddr.h"
54
55
-#ifdef CONFIG_TCG
56
-
57
-#if !defined(CONFIG_USER_ONLY)
58
-/* cputlb.c */
59
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
60
void tlb_protect_code(ram_addr_t ram_addr);
61
void tlb_unprotect_code(ram_addr_t ram_addr);
62
#endif
63
64
-#endif /* CONFIG_TCG */
65
-
66
#ifndef CONFIG_USER_ONLY
67
-
68
void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
69
void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
70
-
71
#endif
72
73
/**
74
@@ -XXX,XX +XXX,XX @@ void tlb_set_page(CPUState *cpu, vaddr addr,
75
hwaddr paddr, int prot,
76
int mmu_idx, vaddr size);
77
78
-#endif
79
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
80
+/**
81
+ * tlb_flush_page:
82
+ * @cpu: CPU whose TLB should be flushed
83
+ * @addr: virtual address of page to be flushed
84
+ *
85
+ * Flush one page from the TLB of the specified CPU, for all
86
+ * MMU indexes.
87
+ */
88
+void tlb_flush_page(CPUState *cpu, vaddr addr);
89
+
90
+/**
91
+ * tlb_flush_page_all_cpus_synced:
92
+ * @cpu: src CPU of the flush
93
+ * @addr: virtual address of page to be flushed
94
+ *
95
+ * Flush one page from the TLB of all CPUs, for all
96
+ * MMU indexes.
97
+ *
98
+ * When this function returns, no CPUs will subsequently perform
99
+ * translations using the flushed TLBs.
100
+ */
101
+void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr);
102
+
103
+/**
104
+ * tlb_flush:
105
+ * @cpu: CPU whose TLB should be flushed
106
+ *
107
+ * Flush the entire TLB for the specified CPU. Most CPU architectures
108
+ * allow the implementation to drop entries from the TLB at any time
109
+ * so this is generally safe. If more selective flushing is required
110
+ * use one of the other functions for efficiency.
111
+ */
112
+void tlb_flush(CPUState *cpu);
113
+
114
+/**
115
+ * tlb_flush_all_cpus_synced:
116
+ * @cpu: src CPU of the flush
117
+ *
118
+ * Flush the entire TLB for all CPUs, for all MMU indexes.
119
+ *
120
+ * When this function returns, no CPUs will subsequently perform
121
+ * translations using the flushed TLBs.
122
+ */
123
+void tlb_flush_all_cpus_synced(CPUState *src_cpu);
124
+
125
+/**
126
+ * tlb_flush_page_by_mmuidx:
127
+ * @cpu: CPU whose TLB should be flushed
128
+ * @addr: virtual address of page to be flushed
129
+ * @idxmap: bitmap of MMU indexes to flush
130
+ *
131
+ * Flush one page from the TLB of the specified CPU, for the specified
132
+ * MMU indexes.
133
+ */
134
+void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr,
135
+ uint16_t idxmap);
136
+
137
+/**
138
+ * tlb_flush_page_by_mmuidx_all_cpus_synced:
139
+ * @cpu: Originating CPU of the flush
140
+ * @addr: virtual address of page to be flushed
141
+ * @idxmap: bitmap of MMU indexes to flush
142
+ *
143
+ * Flush one page from the TLB of all CPUs, for the specified
144
+ * MMU indexes.
145
+ *
146
+ * When this function returns, no CPUs will subsequently perform
147
+ * translations using the flushed TLBs.
148
+ */
149
+void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
150
+ uint16_t idxmap);
151
+
152
+/**
153
+ * tlb_flush_by_mmuidx:
154
+ * @cpu: CPU whose TLB should be flushed
155
+ * @wait: If true ensure synchronisation by exiting the cpu_loop
156
+ * @idxmap: bitmap of MMU indexes to flush
157
+ *
158
+ * Flush all entries from the TLB of the specified CPU, for the specified
159
+ * MMU indexes.
160
+ */
161
+void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
162
+
163
+/**
164
+ * tlb_flush_by_mmuidx_all_cpus_synced:
165
+ * @cpu: Originating CPU of the flush
166
+ * @idxmap: bitmap of MMU indexes to flush
167
+ *
168
+ * Flush all entries from the TLB of all CPUs, for the specified
169
+ * MMU indexes.
170
+ *
171
+ * When this function returns, no CPUs will subsequently perform
172
+ * translations using the flushed TLBs.
173
+ */
174
+void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
175
+
176
+/**
177
+ * tlb_flush_page_bits_by_mmuidx
178
+ * @cpu: CPU whose TLB should be flushed
179
+ * @addr: virtual address of page to be flushed
180
+ * @idxmap: bitmap of mmu indexes to flush
181
+ * @bits: number of significant bits in address
182
+ *
183
+ * Similar to tlb_flush_page_mask, but with a bitmap of indexes.
184
+ */
185
+void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr,
186
+ uint16_t idxmap, unsigned bits);
187
+
188
+/* Similarly, with broadcast and syncing. */
189
+void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
190
+ uint16_t idxmap,
191
+ unsigned bits);
192
+
193
+/**
194
+ * tlb_flush_range_by_mmuidx
195
+ * @cpu: CPU whose TLB should be flushed
196
+ * @addr: virtual address of the start of the range to be flushed
197
+ * @len: length of range to be flushed
198
+ * @idxmap: bitmap of mmu indexes to flush
199
+ * @bits: number of significant bits in address
200
+ *
201
+ * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
202
+ * comparing only the low @bits worth of each virtual page.
203
+ */
204
+void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
205
+ vaddr len, uint16_t idxmap,
206
+ unsigned bits);
207
+
208
+/* Similarly, with broadcast and syncing. */
209
+void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
210
+ vaddr addr,
211
+ vaddr len,
212
+ uint16_t idxmap,
213
+ unsigned bits);
214
+#else
215
+static inline void tlb_flush_page(CPUState *cpu, vaddr addr)
216
+{
217
+}
218
+static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr)
219
+{
220
+}
221
+static inline void tlb_flush(CPUState *cpu)
222
+{
223
+}
224
+static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
225
+{
226
+}
227
+static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
228
+ vaddr addr, uint16_t idxmap)
229
+{
230
+}
231
+
232
+static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
233
+{
234
+}
235
+static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
236
+ vaddr addr,
237
+ uint16_t idxmap)
238
+{
239
+}
240
+static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
241
+ uint16_t idxmap)
242
+{
243
+}
244
+static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
245
+ vaddr addr,
246
+ uint16_t idxmap,
247
+ unsigned bits)
248
+{
249
+}
250
+static inline void
251
+tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
252
+ uint16_t idxmap, unsigned bits)
253
+{
254
+}
255
+static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
256
+ vaddr len, uint16_t idxmap,
257
+ unsigned bits)
258
+{
259
+}
260
+static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
261
+ vaddr addr,
262
+ vaddr len,
263
+ uint16_t idxmap,
264
+ unsigned bits)
265
+{
266
+}
267
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
268
+#endif /* CPUTLB_H */
269
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
270
index XXXXXXX..XXXXXXX 100644
271
--- a/include/exec/exec-all.h
272
+++ b/include/exec/exec-all.h
273
@@ -XXX,XX +XXX,XX @@
274
#include "exec/mmu-access-type.h"
275
#include "exec/translation-block.h"
276
277
-#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
278
-/* cputlb.c */
279
-/**
280
- * tlb_flush_page:
281
- * @cpu: CPU whose TLB should be flushed
282
- * @addr: virtual address of page to be flushed
283
- *
284
- * Flush one page from the TLB of the specified CPU, for all
285
- * MMU indexes.
286
- */
287
-void tlb_flush_page(CPUState *cpu, vaddr addr);
288
-/**
289
- * tlb_flush_page_all_cpus_synced:
290
- * @cpu: src CPU of the flush
291
- * @addr: virtual address of page to be flushed
292
- *
293
- * Flush one page from the TLB of all CPUs, for all
294
- * MMU indexes.
295
- *
296
- * When this function returns, no CPUs will subsequently perform
297
- * translations using the flushed TLBs.
298
- */
299
-void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr);
300
-/**
301
- * tlb_flush:
302
- * @cpu: CPU whose TLB should be flushed
303
- *
304
- * Flush the entire TLB for the specified CPU. Most CPU architectures
305
- * allow the implementation to drop entries from the TLB at any time
306
- * so this is generally safe. If more selective flushing is required
307
- * use one of the other functions for efficiency.
308
- */
309
-void tlb_flush(CPUState *cpu);
310
-/**
311
- * tlb_flush_all_cpus_synced:
312
- * @cpu: src CPU of the flush
313
- *
314
- * Flush the entire TLB for all CPUs, for all MMU indexes.
315
- *
316
- * When this function returns, no CPUs will subsequently perform
317
- * translations using the flushed TLBs.
318
- */
319
-void tlb_flush_all_cpus_synced(CPUState *src_cpu);
320
-/**
321
- * tlb_flush_page_by_mmuidx:
322
- * @cpu: CPU whose TLB should be flushed
323
- * @addr: virtual address of page to be flushed
324
- * @idxmap: bitmap of MMU indexes to flush
325
- *
326
- * Flush one page from the TLB of the specified CPU, for the specified
327
- * MMU indexes.
328
- */
329
-void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr,
330
- uint16_t idxmap);
331
-/**
332
- * tlb_flush_page_by_mmuidx_all_cpus_synced:
333
- * @cpu: Originating CPU of the flush
334
- * @addr: virtual address of page to be flushed
335
- * @idxmap: bitmap of MMU indexes to flush
336
- *
337
- * Flush one page from the TLB of all CPUs, for the specified
338
- * MMU indexes.
339
- *
340
- * When this function returns, no CPUs will subsequently perform
341
- * translations using the flushed TLBs.
342
- */
343
-void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
344
- uint16_t idxmap);
345
-/**
346
- * tlb_flush_by_mmuidx:
347
- * @cpu: CPU whose TLB should be flushed
348
- * @wait: If true ensure synchronisation by exiting the cpu_loop
349
- * @idxmap: bitmap of MMU indexes to flush
350
- *
351
- * Flush all entries from the TLB of the specified CPU, for the specified
352
- * MMU indexes.
353
- */
354
-void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
355
-/**
356
- * tlb_flush_by_mmuidx_all_cpus_synced:
357
- * @cpu: Originating CPU of the flush
358
- * @idxmap: bitmap of MMU indexes to flush
359
- *
360
- * Flush all entries from the TLB of all CPUs, for the specified
361
- * MMU indexes.
362
- *
363
- * When this function returns, no CPUs will subsequently perform
364
- * translations using the flushed TLBs.
365
- */
366
-void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
367
-
368
-/**
369
- * tlb_flush_page_bits_by_mmuidx
370
- * @cpu: CPU whose TLB should be flushed
371
- * @addr: virtual address of page to be flushed
372
- * @idxmap: bitmap of mmu indexes to flush
373
- * @bits: number of significant bits in address
374
- *
375
- * Similar to tlb_flush_page_mask, but with a bitmap of indexes.
376
- */
377
-void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr,
378
- uint16_t idxmap, unsigned bits);
379
-
380
-/* Similarly, with broadcast and syncing. */
381
-void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
382
- (CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits);
383
-
384
-/**
385
- * tlb_flush_range_by_mmuidx
386
- * @cpu: CPU whose TLB should be flushed
387
- * @addr: virtual address of the start of the range to be flushed
388
- * @len: length of range to be flushed
389
- * @idxmap: bitmap of mmu indexes to flush
390
- * @bits: number of significant bits in address
391
- *
392
- * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
393
- * comparing only the low @bits worth of each virtual page.
394
- */
395
-void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
396
- vaddr len, uint16_t idxmap,
397
- unsigned bits);
398
-
399
-/* Similarly, with broadcast and syncing. */
400
-void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
401
- vaddr addr,
402
- vaddr len,
403
- uint16_t idxmap,
404
- unsigned bits);
405
-
406
-#else
407
-static inline void tlb_flush_page(CPUState *cpu, vaddr addr)
408
-{
409
-}
410
-static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr)
411
-{
412
-}
413
-static inline void tlb_flush(CPUState *cpu)
414
-{
415
-}
416
-static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
417
-{
418
-}
419
-static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
420
- vaddr addr, uint16_t idxmap)
421
-{
422
-}
423
-
424
-static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
425
-{
426
-}
427
-static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
428
- vaddr addr,
429
- uint16_t idxmap)
430
-{
431
-}
432
-static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
433
- uint16_t idxmap)
434
-{
435
-}
436
-static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
437
- vaddr addr,
438
- uint16_t idxmap,
439
- unsigned bits)
440
-{
441
-}
442
-static inline void
443
-tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
444
- uint16_t idxmap, unsigned bits)
445
-{
446
-}
447
-static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
448
- vaddr len, uint16_t idxmap,
449
- unsigned bits)
450
-{
451
-}
452
-static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
453
- vaddr addr,
454
- vaddr len,
455
- uint16_t idxmap,
456
- unsigned bits)
457
-{
458
-}
459
-#endif
460
-
461
#if defined(CONFIG_TCG)
462
463
/**
464
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
465
index XXXXXXX..XXXXXXX 100644
466
--- a/accel/tcg/tcg-accel-ops.c
467
+++ b/accel/tcg/tcg-accel-ops.c
468
@@ -XXX,XX +XXX,XX @@
469
#include "qemu/main-loop.h"
470
#include "qemu/guest-random.h"
471
#include "qemu/timer.h"
472
-#include "exec/exec-all.h"
473
+#include "exec/cputlb.h"
474
#include "exec/hwaddr.h"
475
#include "exec/tb-flush.h"
476
#include "exec/translation-block.h"
477
diff --git a/cpu-target.c b/cpu-target.c
478
index XXXXXXX..XXXXXXX 100644
479
--- a/cpu-target.c
480
+++ b/cpu-target.c
481
@@ -XXX,XX +XXX,XX @@
482
#include "exec/tswap.h"
483
#include "exec/replay-core.h"
484
#include "exec/cpu-common.h"
485
+#include "exec/cputlb.h"
486
#include "exec/exec-all.h"
487
#include "exec/tb-flush.h"
488
#include "exec/log.h"
489
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
490
index XXXXXXX..XXXXXXX 100644
491
--- a/hw/intc/armv7m_nvic.c
492
+++ b/hw/intc/armv7m_nvic.c
493
@@ -XXX,XX +XXX,XX @@
494
#include "system/runstate.h"
495
#include "target/arm/cpu.h"
496
#include "target/arm/cpu-features.h"
497
-#include "exec/exec-all.h"
498
+#include "exec/cputlb.h"
499
#include "exec/memop.h"
500
#include "qemu/log.h"
501
#include "qemu/module.h"
502
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
503
index XXXXXXX..XXXXXXX 100644
504
--- a/hw/ppc/spapr_nested.c
505
+++ b/hw/ppc/spapr_nested.c
506
@@ -XXX,XX +XXX,XX @@
507
#include "qemu/osdep.h"
508
#include "qemu/cutils.h"
509
#include "exec/exec-all.h"
510
+#include "exec/cputlb.h"
511
#include "helper_regs.h"
512
#include "hw/ppc/ppc.h"
513
#include "hw/ppc/spapr.h"
514
diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c
515
index XXXXXXX..XXXXXXX 100644
516
--- a/hw/sh4/sh7750.c
517
+++ b/hw/sh4/sh7750.c
518
@@ -XXX,XX +XXX,XX @@
519
#include "hw/sh4/sh_intc.h"
520
#include "hw/timer/tmu012.h"
521
#include "exec/exec-all.h"
522
+#include "exec/cputlb.h"
523
#include "trace.h"
524
525
typedef struct SH7750State {
526
diff --git a/system/watchpoint.c b/system/watchpoint.c
527
index XXXXXXX..XXXXXXX 100644
528
--- a/system/watchpoint.c
529
+++ b/system/watchpoint.c
530
@@ -XXX,XX +XXX,XX @@
531
532
#include "qemu/osdep.h"
533
#include "qemu/error-report.h"
534
-#include "exec/exec-all.h"
535
+#include "exec/cputlb.h"
536
+#include "exec/target_page.h"
537
#include "hw/core/cpu.h"
538
539
/* Add a watchpoint. */
540
diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c
541
index XXXXXXX..XXXXXXX 100644
542
--- a/target/alpha/sys_helper.c
543
+++ b/target/alpha/sys_helper.c
544
@@ -XXX,XX +XXX,XX @@
545
546
#include "qemu/osdep.h"
547
#include "cpu.h"
548
-#include "exec/exec-all.h"
549
+#include "exec/cputlb.h"
550
#include "exec/tb-flush.h"
551
#include "exec/helper-proto.h"
552
#include "system/runstate.h"
553
diff --git a/target/arm/helper.c b/target/arm/helper.c
554
index XXXXXXX..XXXXXXX 100644
555
--- a/target/arm/helper.c
556
+++ b/target/arm/helper.c
557
@@ -XXX,XX +XXX,XX @@
558
#include "qemu/timer.h"
559
#include "qemu/bitops.h"
560
#include "qemu/qemu-print.h"
561
+#include "exec/cputlb.h"
562
#include "exec/exec-all.h"
563
#include "exec/translation-block.h"
564
#include "hw/irq.h"
565
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
566
index XXXXXXX..XXXXXXX 100644
567
--- a/target/arm/tcg/tlb-insns.c
568
+++ b/target/arm/tcg/tlb-insns.c
569
@@ -XXX,XX +XXX,XX @@
570
*/
571
#include "qemu/osdep.h"
572
#include "qemu/log.h"
573
-#include "exec/exec-all.h"
574
+#include "exec/cputlb.h"
575
#include "cpu.h"
576
#include "internals.h"
577
#include "cpu-features.h"
578
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
579
index XXXXXXX..XXXXXXX 100644
580
--- a/target/hppa/mem_helper.c
581
+++ b/target/hppa/mem_helper.c
582
@@ -XXX,XX +XXX,XX @@
583
#include "qemu/log.h"
584
#include "cpu.h"
585
#include "exec/exec-all.h"
586
+#include "exec/cputlb.h"
587
#include "exec/page-protection.h"
588
#include "exec/helper-proto.h"
589
#include "hw/core/cpu.h"
590
diff --git a/target/i386/helper.c b/target/i386/helper.c
591
index XXXXXXX..XXXXXXX 100644
592
--- a/target/i386/helper.c
593
+++ b/target/i386/helper.c
594
@@ -XXX,XX +XXX,XX @@
595
#include "qemu/osdep.h"
596
#include "qapi/qapi-events-run-state.h"
597
#include "cpu.h"
598
-#include "exec/exec-all.h"
599
+#include "exec/cputlb.h"
600
#include "exec/translation-block.h"
601
#include "system/runstate.h"
602
#ifndef CONFIG_USER_ONLY
603
diff --git a/target/i386/machine.c b/target/i386/machine.c
604
index XXXXXXX..XXXXXXX 100644
605
--- a/target/i386/machine.c
606
+++ b/target/i386/machine.c
607
@@ -XXX,XX +XXX,XX @@
608
#include "qemu/osdep.h"
609
#include "cpu.h"
610
-#include "exec/exec-all.h"
611
+#include "exec/cputlb.h"
612
#include "hw/isa/isa.h"
613
#include "migration/cpu.h"
614
#include "kvm/hyperv.h"
615
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
616
index XXXXXXX..XXXXXXX 100644
617
--- a/target/i386/tcg/fpu_helper.c
618
+++ b/target/i386/tcg/fpu_helper.c
619
@@ -XXX,XX +XXX,XX @@
620
#include <math.h>
621
#include "cpu.h"
622
#include "tcg-cpu.h"
623
-#include "exec/exec-all.h"
624
+#include "exec/cputlb.h"
625
#include "exec/cpu_ldst.h"
626
#include "exec/helper-proto.h"
627
#include "fpu/softfloat.h"
628
diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c
629
index XXXXXXX..XXXXXXX 100644
630
--- a/target/i386/tcg/misc_helper.c
631
+++ b/target/i386/tcg/misc_helper.c
632
@@ -XXX,XX +XXX,XX @@
633
#include "qemu/log.h"
634
#include "cpu.h"
635
#include "exec/helper-proto.h"
636
-#include "exec/exec-all.h"
637
+#include "exec/cputlb.h"
638
#include "helper-tcg.h"
639
640
/*
641
diff --git a/target/i386/tcg/system/misc_helper.c b/target/i386/tcg/system/misc_helper.c
642
index XXXXXXX..XXXXXXX 100644
643
--- a/target/i386/tcg/system/misc_helper.c
644
+++ b/target/i386/tcg/system/misc_helper.c
645
@@ -XXX,XX +XXX,XX @@
646
#include "exec/helper-proto.h"
647
#include "exec/cpu_ldst.h"
648
#include "exec/address-spaces.h"
649
-#include "exec/exec-all.h"
650
+#include "exec/cputlb.h"
651
#include "tcg/helper-tcg.h"
652
#include "hw/i386/apic.h"
653
654
diff --git a/target/i386/tcg/system/svm_helper.c b/target/i386/tcg/system/svm_helper.c
655
index XXXXXXX..XXXXXXX 100644
656
--- a/target/i386/tcg/system/svm_helper.c
657
+++ b/target/i386/tcg/system/svm_helper.c
658
@@ -XXX,XX +XXX,XX @@
659
#include "qemu/log.h"
660
#include "cpu.h"
661
#include "exec/helper-proto.h"
662
-#include "exec/exec-all.h"
663
+#include "exec/cputlb.h"
664
#include "exec/cpu_ldst.h"
665
#include "tcg/helper-tcg.h"
666
667
diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c
668
index XXXXXXX..XXXXXXX 100644
669
--- a/target/loongarch/tcg/csr_helper.c
670
+++ b/target/loongarch/tcg/csr_helper.c
671
@@ -XXX,XX +XXX,XX @@
672
#include "internals.h"
673
#include "qemu/host-utils.h"
674
#include "exec/helper-proto.h"
675
-#include "exec/exec-all.h"
676
+#include "exec/cputlb.h"
677
#include "exec/cpu_ldst.h"
678
#include "hw/irq.h"
679
#include "cpu-csr.h"
680
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
681
index XXXXXXX..XXXXXXX 100644
682
--- a/target/microblaze/mmu.c
683
+++ b/target/microblaze/mmu.c
684
@@ -XXX,XX +XXX,XX @@
685
#include "qemu/osdep.h"
686
#include "qemu/log.h"
687
#include "cpu.h"
688
-#include "exec/exec-all.h"
689
+#include "exec/cputlb.h"
690
#include "exec/page-protection.h"
691
692
static unsigned int tlb_decode_size(unsigned int f)
693
diff --git a/target/mips/system/cp0.c b/target/mips/system/cp0.c
694
index XXXXXXX..XXXXXXX 100644
695
--- a/target/mips/system/cp0.c
696
+++ b/target/mips/system/cp0.c
697
@@ -XXX,XX +XXX,XX @@
698
#include "qemu/osdep.h"
699
#include "cpu.h"
700
#include "internal.h"
701
-#include "exec/exec-all.h"
702
+#include "exec/cputlb.h"
703
704
/* Called for updates to CP0_Status. */
705
void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
706
diff --git a/target/mips/tcg/system/cp0_helper.c b/target/mips/tcg/system/cp0_helper.c
707
index XXXXXXX..XXXXXXX 100644
708
--- a/target/mips/tcg/system/cp0_helper.c
709
+++ b/target/mips/tcg/system/cp0_helper.c
710
@@ -XXX,XX +XXX,XX @@
711
#include "internal.h"
712
#include "qemu/host-utils.h"
713
#include "exec/helper-proto.h"
714
-#include "exec/exec-all.h"
715
+#include "exec/cputlb.h"
716
717
718
/* SMP helpers. */
719
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
720
index XXXXXXX..XXXXXXX 100644
721
--- a/target/openrisc/sys_helper.c
722
+++ b/target/openrisc/sys_helper.c
723
@@ -XXX,XX +XXX,XX @@
724
#include "qemu/osdep.h"
725
#include "cpu.h"
726
#include "exec/exec-all.h"
727
+#include "exec/cputlb.h"
728
#include "exec/helper-proto.h"
729
#include "exception.h"
730
#ifndef CONFIG_USER_ONLY
731
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
732
index XXXXXXX..XXXXXXX 100644
733
--- a/target/ppc/helper_regs.c
734
+++ b/target/ppc/helper_regs.c
735
@@ -XXX,XX +XXX,XX @@
736
#include "qemu/osdep.h"
737
#include "cpu.h"
738
#include "qemu/main-loop.h"
739
-#include "exec/exec-all.h"
740
+#include "exec/cputlb.h"
741
#include "system/kvm.h"
742
#include "system/tcg.h"
743
#include "helper_regs.h"
744
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
745
index XXXXXXX..XXXXXXX 100644
746
--- a/target/ppc/misc_helper.c
747
+++ b/target/ppc/misc_helper.c
748
@@ -XXX,XX +XXX,XX @@
749
#include "qemu/log.h"
750
#include "cpu.h"
751
#include "exec/exec-all.h"
752
+#include "exec/cputlb.h"
753
#include "exec/helper-proto.h"
754
#include "qemu/error-report.h"
755
#include "qemu/main-loop.h"
756
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
757
index XXXXXXX..XXXXXXX 100644
758
--- a/target/riscv/csr.c
759
+++ b/target/riscv/csr.c
760
@@ -XXX,XX +XXX,XX @@
761
#include "pmu.h"
762
#include "time_helper.h"
763
#include "exec/exec-all.h"
764
+#include "exec/cputlb.h"
765
#include "exec/tb-flush.h"
766
#include "system/cpu-timers.h"
767
#include "qemu/guest-random.h"
768
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
769
index XXXXXXX..XXXXXXX 100644
770
--- a/target/riscv/op_helper.c
771
+++ b/target/riscv/op_helper.c
772
@@ -XXX,XX +XXX,XX @@
773
#include "cpu.h"
774
#include "internals.h"
775
#include "exec/exec-all.h"
776
+#include "exec/cputlb.h"
777
#include "exec/cpu_ldst.h"
778
#include "exec/helper-proto.h"
779
#include "trace.h"
780
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
781
index XXXXXXX..XXXXXXX 100644
782
--- a/target/riscv/pmp.c
783
+++ b/target/riscv/pmp.c
784
@@ -XXX,XX +XXX,XX @@
785
#include "qapi/error.h"
786
#include "cpu.h"
787
#include "trace.h"
788
-#include "exec/exec-all.h"
789
+#include "exec/cputlb.h"
790
#include "exec/page-protection.h"
791
792
static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
793
diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c
794
index XXXXXXX..XXXXXXX 100644
795
--- a/target/s390x/gdbstub.c
796
+++ b/target/s390x/gdbstub.c
797
@@ -XXX,XX +XXX,XX @@
798
#include "qemu/osdep.h"
799
#include "cpu.h"
800
#include "s390x-internal.h"
801
-#include "exec/exec-all.h"
802
+#include "exec/cputlb.h"
803
#include "exec/gdbstub.h"
804
#include "gdbstub/helpers.h"
805
#include "qemu/bitops.h"
806
diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
807
index XXXXXXX..XXXXXXX 100644
808
--- a/target/s390x/sigp.c
809
+++ b/target/s390x/sigp.c
810
@@ -XXX,XX +XXX,XX @@
811
#include "system/hw_accel.h"
812
#include "system/runstate.h"
813
#include "exec/address-spaces.h"
814
+#include "exec/cputlb.h"
815
#include "exec/exec-all.h"
816
#include "system/tcg.h"
817
#include "trace.h"
818
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
819
index XXXXXXX..XXXXXXX 100644
820
--- a/target/s390x/tcg/mem_helper.c
821
+++ b/target/s390x/tcg/mem_helper.c
822
@@ -XXX,XX +XXX,XX @@
823
#include "exec/helper-proto.h"
824
#include "exec/cpu-common.h"
825
#include "exec/exec-all.h"
826
+#include "exec/cputlb.h"
827
#include "exec/page-protection.h"
828
#include "exec/cpu_ldst.h"
829
#include "accel/tcg/cpu-ops.h"
830
diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c
831
index XXXXXXX..XXXXXXX 100644
832
--- a/target/s390x/tcg/misc_helper.c
833
+++ b/target/s390x/tcg/misc_helper.c
834
@@ -XXX,XX +XXX,XX @@
835
#include "exec/helper-proto.h"
836
#include "qemu/timer.h"
837
#include "exec/exec-all.h"
838
+#include "exec/cputlb.h"
839
#include "exec/cpu_ldst.h"
840
#include "qapi/error.h"
841
#include "tcg_s390x.h"
842
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
843
index XXXXXXX..XXXXXXX 100644
844
--- a/target/sparc/ldst_helper.c
845
+++ b/target/sparc/ldst_helper.c
846
@@ -XXX,XX +XXX,XX @@
847
#include "tcg/tcg.h"
848
#include "exec/helper-proto.h"
849
#include "exec/exec-all.h"
850
+#include "exec/cputlb.h"
851
#include "exec/page-protection.h"
852
#include "exec/cpu_ldst.h"
853
#ifdef CONFIG_USER_ONLY
854
diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
855
index XXXXXXX..XXXXXXX 100644
856
--- a/target/xtensa/mmu_helper.c
857
+++ b/target/xtensa/mmu_helper.c
858
@@ -XXX,XX +XXX,XX @@
859
#include "cpu.h"
860
#include "exec/helper-proto.h"
861
#include "qemu/host-utils.h"
862
+#include "exec/cputlb.h"
863
#include "exec/exec-all.h"
864
#include "exec/page-protection.h"
865
866
--
867
2.43.0
868
869
diff view generated by jsdifflib
New patch
[PULL 12/23] system: Build watchpoint.c once
1
Now that watchpoint.c uses cputlb.h instead of exec-all.h,
2
it can be built once.
1
3
4
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
system/meson.build | 2 +-
10
1 file changed, 1 insertion(+), 1 deletion(-)
11
12
diff --git a/system/meson.build b/system/meson.build
13
index XXXXXXX..XXXXXXX 100644
14
--- a/system/meson.build
15
+++ b/system/meson.build
16
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: [files(
17
'ioport.c',
18
'memory.c',
19
'physmem.c',
20
- 'watchpoint.c',
21
)])
22
23
system_ss.add(files(
24
@@ -XXX,XX +XXX,XX @@ system_ss.add(files(
25
'runstate.c',
26
'tpm-hmp-cmds.c',
27
'vl.c',
28
+ 'watchpoint.c',
29
), sdl, libpmem, libdaxctl)
30
31
if have_tpm
32
--
33
2.43.0
34
35
diff view generated by jsdifflib
New patch
[PULL 13/23] accel/tcg: Build tcg-accel-ops.c once
1
Now that tcg-accel-ops.c uses cputlb.h instead of exec-all.h,
2
it can be built once.
1
3
4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
accel/tcg/meson.build | 2 +-
8
1 file changed, 1 insertion(+), 1 deletion(-)
9
10
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
11
index XXXXXXX..XXXXXXX 100644
12
--- a/accel/tcg/meson.build
13
+++ b/accel/tcg/meson.build
14
@@ -XXX,XX +XXX,XX @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
15
16
specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
17
'cputlb.c',
18
- 'tcg-accel-ops.c',
19
'tcg-accel-ops-mttcg.c',
20
'tcg-accel-ops-icount.c',
21
'tcg-accel-ops-rr.c',
22
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
23
system_ss.add(when: ['CONFIG_TCG'], if_true: files(
24
'icount-common.c',
25
'monitor.c',
26
+ 'tcg-accel-ops.c',
27
'watchpoint.c',
28
))
29
--
30
2.43.0
diff view generated by jsdifflib
New patch
[PULL 14/23] accel/tcg: Build tcg-accel-ops-icount.c once
1
All that is required is to avoid including exec-all.h.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
accel/tcg/tcg-accel-ops-icount.c | 2 +-
7
accel/tcg/meson.build | 2 +-
8
2 files changed, 2 insertions(+), 2 deletions(-)
9
10
diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/accel/tcg/tcg-accel-ops-icount.c
13
+++ b/accel/tcg/tcg-accel-ops-icount.c
14
@@ -XXX,XX +XXX,XX @@
15
#include "system/cpu-timers.h"
16
#include "qemu/main-loop.h"
17
#include "qemu/guest-random.h"
18
-#include "exec/exec-all.h"
19
+#include "hw/core/cpu.h"
20
21
#include "tcg-accel-ops.h"
22
#include "tcg-accel-ops-icount.h"
23
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
24
index XXXXXXX..XXXXXXX 100644
25
--- a/accel/tcg/meson.build
26
+++ b/accel/tcg/meson.build
27
@@ -XXX,XX +XXX,XX @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
28
specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
29
'cputlb.c',
30
'tcg-accel-ops-mttcg.c',
31
- 'tcg-accel-ops-icount.c',
32
'tcg-accel-ops-rr.c',
33
))
34
35
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files(
36
'icount-common.c',
37
'monitor.c',
38
'tcg-accel-ops.c',
39
+ 'tcg-accel-ops-icount.c',
40
'watchpoint.c',
41
))
42
--
43
2.43.0
diff view generated by jsdifflib
New patch
[PULL 15/23] accel/tcg: Build tcg-accel-ops-rr.c once
1
All that is required is to use cpu-common.h instead of exec-all.h.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
accel/tcg/tcg-accel-ops-rr.c | 2 +-
7
accel/tcg/meson.build | 2 +-
8
2 files changed, 2 insertions(+), 2 deletions(-)
9
10
diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/accel/tcg/tcg-accel-ops-rr.c
13
+++ b/accel/tcg/tcg-accel-ops-rr.c
14
@@ -XXX,XX +XXX,XX @@
15
#include "qemu/main-loop.h"
16
#include "qemu/notify.h"
17
#include "qemu/guest-random.h"
18
-#include "exec/exec-all.h"
19
+#include "exec/cpu-common.h"
20
#include "tcg/startup.h"
21
#include "tcg-accel-ops.h"
22
#include "tcg-accel-ops-rr.h"
23
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
24
index XXXXXXX..XXXXXXX 100644
25
--- a/accel/tcg/meson.build
26
+++ b/accel/tcg/meson.build
27
@@ -XXX,XX +XXX,XX @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
28
specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
29
'cputlb.c',
30
'tcg-accel-ops-mttcg.c',
31
- 'tcg-accel-ops-rr.c',
32
))
33
34
system_ss.add(when: ['CONFIG_TCG'], if_true: files(
35
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files(
36
'monitor.c',
37
'tcg-accel-ops.c',
38
'tcg-accel-ops-icount.c',
39
+ 'tcg-accel-ops-rr.c',
40
'watchpoint.c',
41
))
42
--
43
2.43.0
diff view generated by jsdifflib
New patch
[PULL 16/23] accel/tcg: Build tcg-accel-ops-mttcg.c once
1
All that is required is to avoid including exec-all.h.
1
2
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
accel/tcg/tcg-accel-ops-mttcg.c | 1 -
7
accel/tcg/meson.build | 2 +-
8
2 files changed, 1 insertion(+), 2 deletions(-)
9
10
diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/accel/tcg/tcg-accel-ops-mttcg.c
13
+++ b/accel/tcg/tcg-accel-ops-mttcg.c
14
@@ -XXX,XX +XXX,XX @@
15
#include "qemu/main-loop.h"
16
#include "qemu/notify.h"
17
#include "qemu/guest-random.h"
18
-#include "exec/exec-all.h"
19
#include "hw/boards.h"
20
#include "tcg/startup.h"
21
#include "tcg-accel-ops.h"
22
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
23
index XXXXXXX..XXXXXXX 100644
24
--- a/accel/tcg/meson.build
25
+++ b/accel/tcg/meson.build
26
@@ -XXX,XX +XXX,XX @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
27
28
specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
29
'cputlb.c',
30
- 'tcg-accel-ops-mttcg.c',
31
))
32
33
system_ss.add(when: ['CONFIG_TCG'], if_true: files(
34
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files(
35
'monitor.c',
36
'tcg-accel-ops.c',
37
'tcg-accel-ops-icount.c',
38
+ 'tcg-accel-ops-mttcg.c',
39
'tcg-accel-ops-rr.c',
40
'watchpoint.c',
41
))
42
--
43
2.43.0
diff view generated by jsdifflib
New patch
[PULL 17/23] accel/tcg: Restrict GETPC_ADJ to 'tb-internal.h'
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
GETPC_ADJ is only used within accel/tcg/, no need to
4
expose it to all the code base.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-ID: <20250308072348.65723-2-philmd@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
10
accel/tcg/tb-internal.h | 11 +++++++++++
11
include/exec/exec-all.h | 9 ---------
12
2 files changed, 11 insertions(+), 9 deletions(-)
13
14
diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/accel/tcg/tb-internal.h
17
+++ b/accel/tcg/tb-internal.h
18
@@ -XXX,XX +XXX,XX @@
19
#include "exec/exec-all.h"
20
#include "exec/translation-block.h"
21
22
+/*
23
+ * The true return address will often point to a host insn that is part of
24
+ * the next translated guest insn. Adjust the address backward to point to
25
+ * the middle of the call insn. Subtracting one would do the job except for
26
+ * several compressed mode architectures (arm, mips) which set the low bit
27
+ * to indicate the compressed mode; subtracting two works around that. It
28
+ * is also the case that there are no host isas that contain a call insn
29
+ * smaller than 4 bytes, so we don't worry about special-casing this.
30
+ */
31
+#define GETPC_ADJ 2
32
+
33
#ifdef CONFIG_SOFTMMU
34
35
#define CPU_TLB_DYN_MIN_BITS 6
36
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/exec/exec-all.h
39
+++ b/include/exec/exec-all.h
40
@@ -XXX,XX +XXX,XX @@ extern __thread uintptr_t tci_tb_ptr;
41
((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
42
#endif
43
44
-/* The true return address will often point to a host insn that is part of
45
- the next translated guest insn. Adjust the address backward to point to
46
- the middle of the call insn. Subtracting one would do the job except for
47
- several compressed mode architectures (arm, mips) which set the low bit
48
- to indicate the compressed mode; subtracting two works around that. It
49
- is also the case that there are no host isas that contain a call insn
50
- smaller than 4 bytes, so we don't worry about special-casing this. */
51
-#define GETPC_ADJ 2
52
-
53
#if !defined(CONFIG_USER_ONLY)
54
55
/**
56
--
57
2.43.0
58
59
diff view generated by jsdifflib
New patch
[PULL 18/23] accel/tcg: Split out getpc.h
1
Split out GETPC to a target-independent header.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Message-ID: <20250308072348.65723-3-philmd@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
include/accel/tcg/getpc.h | 24 ++++++++++++++++++++++++
10
include/exec/exec-all.h | 10 +---------
11
2 files changed, 25 insertions(+), 9 deletions(-)
12
create mode 100644 include/accel/tcg/getpc.h
13
14
diff --git a/include/accel/tcg/getpc.h b/include/accel/tcg/getpc.h
15
new file mode 100644
16
index XXXXXXX..XXXXXXX
17
--- /dev/null
18
+++ b/include/accel/tcg/getpc.h
19
@@ -XXX,XX +XXX,XX @@
20
+/*
21
+ * Get host pc for helper unwinding.
22
+ *
23
+ * Copyright (c) 2003 Fabrice Bellard
24
+ * SPDX-License-Identifier: LGPL-2.1-or-later
25
+ */
26
+
27
+#ifndef ACCEL_TCG_GETPC_H
28
+#define ACCEL_TCG_GETPC_H
29
+
30
+#ifndef CONFIG_TCG
31
+#error Can only include this header with TCG
32
+#endif
33
+
34
+/* GETPC is the true target of the return instruction that we'll execute. */
35
+#ifdef CONFIG_TCG_INTERPRETER
36
+extern __thread uintptr_t tci_tb_ptr;
37
+# define GETPC() tci_tb_ptr
38
+#else
39
+# define GETPC() \
40
+ ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
41
+#endif
42
+
43
+#endif /* ACCEL_TCG_GETPC_H */
44
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/include/exec/exec-all.h
47
+++ b/include/exec/exec-all.h
48
@@ -XXX,XX +XXX,XX @@
49
#include "exec/translation-block.h"
50
51
#if defined(CONFIG_TCG)
52
+#include "accel/tcg/getpc.h"
53
54
/**
55
* probe_access:
56
@@ -XXX,XX +XXX,XX @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
57
void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last);
58
void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
59
60
-/* GETPC is the true target of the return instruction that we'll execute. */
61
-#if defined(CONFIG_TCG_INTERPRETER)
62
-extern __thread uintptr_t tci_tb_ptr;
63
-# define GETPC() tci_tb_ptr
64
-#else
65
-# define GETPC() \
66
- ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
67
-#endif
68
-
69
#if !defined(CONFIG_USER_ONLY)
70
71
/**
72
--
73
2.43.0
74
75
diff view generated by jsdifflib
New patch
[PULL 19/23] qemu/atomic: Rename atomic128-cas.h headers using .h.inc suffix
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Since commit 139c1837db ("meson: rename included C source files
4
to .c.inc"), QEMU standard procedure for included C files is to
5
use *.c.inc.
6
7
Besides, since commit 6a0057aa22 ("docs/devel: make a statement
8
about includes") this is documented in the Coding Style:
9
10
If you do use template header files they should be named with
11
the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are
12
being included for expansion.
13
14
Therefore rename 'atomic128-cas.h' as 'atomic128-cas.h.inc'.
15
16
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
17
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
18
Message-ID: <20241212141018.59428-2-philmd@linaro.org>
19
---
20
host/include/aarch64/host/atomic128-cas.h | 2 +-
21
include/qemu/atomic128.h | 2 +-
22
.../generic/host/{atomic128-cas.h => atomic128-cas.h.inc} | 0
23
3 files changed, 2 insertions(+), 2 deletions(-)
24
rename host/include/generic/host/{atomic128-cas.h => atomic128-cas.h.inc} (100%)
25
26
diff --git a/host/include/aarch64/host/atomic128-cas.h b/host/include/aarch64/host/atomic128-cas.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/host/include/aarch64/host/atomic128-cas.h
29
+++ b/host/include/aarch64/host/atomic128-cas.h
30
@@ -XXX,XX +XXX,XX @@
31
32
/* Through gcc 10, aarch64 has no support for 128-bit atomics. */
33
#if defined(CONFIG_ATOMIC128) || defined(CONFIG_CMPXCHG128)
34
-#include "host/include/generic/host/atomic128-cas.h"
35
+#include "host/include/generic/host/atomic128-cas.h.inc"
36
#else
37
static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new)
38
{
39
diff --git a/include/qemu/atomic128.h b/include/qemu/atomic128.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/include/qemu/atomic128.h
42
+++ b/include/qemu/atomic128.h
43
@@ -XXX,XX +XXX,XX @@
44
* Therefore, special case each platform.
45
*/
46
47
-#include "host/atomic128-cas.h"
48
+#include "host/atomic128-cas.h.inc"
49
#include "host/atomic128-ldst.h"
50
51
#endif /* QEMU_ATOMIC128_H */
52
diff --git a/host/include/generic/host/atomic128-cas.h b/host/include/generic/host/atomic128-cas.h.inc
53
similarity index 100%
54
rename from host/include/generic/host/atomic128-cas.h
55
rename to host/include/generic/host/atomic128-cas.h.inc
56
--
57
2.43.0
58
59
diff view generated by jsdifflib
New patch
[PULL 20/23] qemu/atomic: Rename atomic128-ldst.h headers using .h.inc suffix
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Since commit 139c1837db ("meson: rename included C source files
4
to .c.inc"), QEMU standard procedure for included C files is to
5
use *.c.inc.
6
7
Besides, since commit 6a0057aa22 ("docs/devel: make a statement
8
about includes") this is documented in the Coding Style:
9
10
If you do use template header files they should be named with
11
the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are
12
being included for expansion.
13
14
Therefore rename 'atomic128-ldst.h' as 'atomic128-ldst.h.inc'.
15
16
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
17
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
18
Message-ID: <20241212141018.59428-3-philmd@linaro.org>
19
---
20
include/qemu/atomic128.h | 2 +-
21
.../aarch64/host/{atomic128-ldst.h => atomic128-ldst.h.inc} | 0
22
.../generic/host/{atomic128-ldst.h => atomic128-ldst.h.inc} | 0
23
.../loongarch64/host/{atomic128-ldst.h => atomic128-ldst.h.inc} | 0
24
.../x86_64/host/{atomic128-ldst.h => atomic128-ldst.h.inc} | 2 +-
25
host/include/x86_64/host/load-extract-al16-al8.h.inc | 2 +-
26
6 files changed, 3 insertions(+), 3 deletions(-)
27
rename host/include/aarch64/host/{atomic128-ldst.h => atomic128-ldst.h.inc} (100%)
28
rename host/include/generic/host/{atomic128-ldst.h => atomic128-ldst.h.inc} (100%)
29
rename host/include/loongarch64/host/{atomic128-ldst.h => atomic128-ldst.h.inc} (100%)
30
rename host/include/x86_64/host/{atomic128-ldst.h => atomic128-ldst.h.inc} (96%)
31
32
diff --git a/include/qemu/atomic128.h b/include/qemu/atomic128.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/include/qemu/atomic128.h
35
+++ b/include/qemu/atomic128.h
36
@@ -XXX,XX +XXX,XX @@
37
*/
38
39
#include "host/atomic128-cas.h.inc"
40
-#include "host/atomic128-ldst.h"
41
+#include "host/atomic128-ldst.h.inc"
42
43
#endif /* QEMU_ATOMIC128_H */
44
diff --git a/host/include/aarch64/host/atomic128-ldst.h b/host/include/aarch64/host/atomic128-ldst.h.inc
45
similarity index 100%
46
rename from host/include/aarch64/host/atomic128-ldst.h
47
rename to host/include/aarch64/host/atomic128-ldst.h.inc
48
diff --git a/host/include/generic/host/atomic128-ldst.h b/host/include/generic/host/atomic128-ldst.h.inc
49
similarity index 100%
50
rename from host/include/generic/host/atomic128-ldst.h
51
rename to host/include/generic/host/atomic128-ldst.h.inc
52
diff --git a/host/include/loongarch64/host/atomic128-ldst.h b/host/include/loongarch64/host/atomic128-ldst.h.inc
53
similarity index 100%
54
rename from host/include/loongarch64/host/atomic128-ldst.h
55
rename to host/include/loongarch64/host/atomic128-ldst.h.inc
56
diff --git a/host/include/x86_64/host/atomic128-ldst.h b/host/include/x86_64/host/atomic128-ldst.h.inc
57
similarity index 96%
58
rename from host/include/x86_64/host/atomic128-ldst.h
59
rename to host/include/x86_64/host/atomic128-ldst.h.inc
60
index XXXXXXX..XXXXXXX 100644
61
--- a/host/include/x86_64/host/atomic128-ldst.h
62
+++ b/host/include/x86_64/host/atomic128-ldst.h.inc
63
@@ -XXX,XX +XXX,XX @@ static inline void atomic16_set(Int128 *ptr, Int128 val)
64
}
65
#else
66
/* Provide QEMU_ERROR stubs. */
67
-#include "host/include/generic/host/atomic128-ldst.h"
68
+#include "host/include/generic/host/atomic128-ldst.h.inc"
69
#endif
70
71
#endif /* X86_64_ATOMIC128_LDST_H */
72
diff --git a/host/include/x86_64/host/load-extract-al16-al8.h.inc b/host/include/x86_64/host/load-extract-al16-al8.h.inc
73
index XXXXXXX..XXXXXXX 100644
74
--- a/host/include/x86_64/host/load-extract-al16-al8.h.inc
75
+++ b/host/include/x86_64/host/load-extract-al16-al8.h.inc
76
@@ -XXX,XX +XXX,XX @@
77
#define X86_64_LOAD_EXTRACT_AL16_AL8_H
78
79
#ifdef CONFIG_INT128_TYPE
80
-#include "host/atomic128-ldst.h"
81
+#include "host/atomic128-ldst.h.inc"
82
83
/**
84
* load_atom_extract_al16_or_al8:
85
--
86
2.43.0
87
88
diff view generated by jsdifflib
New patch
[PULL 21/23] qemu/atomic128: Include missing 'qemu/atomic.h' header
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
qatomic_cmpxchg__nocheck() is declared in "qemu/atomic.h".
4
Include it in order to avoid when refactoring unrelated headers:
5
6
In file included from ../../accel/tcg/tcg-runtime-gvec.c:22:
7
In file included from include/exec/helper-proto-common.h:10:
8
In file included from include/qemu/atomic128.h:61:
9
host/include/generic/host/atomic128-cas.h.inc:23:11: error: call to undeclared function 'qatomic_cmpxchg__nocheck'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
10
23 | r.i = qatomic_cmpxchg__nocheck(ptr_align, c.i, n.i);
11
| ^
12
1 error generated.
13
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-ID: <20241212141018.59428-4-philmd@linaro.org>
18
---
19
include/qemu/atomic128.h | 1 +
20
1 file changed, 1 insertion(+)
21
22
diff --git a/include/qemu/atomic128.h b/include/qemu/atomic128.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/include/qemu/atomic128.h
25
+++ b/include/qemu/atomic128.h
26
@@ -XXX,XX +XXX,XX @@
27
#ifndef QEMU_ATOMIC128_H
28
#define QEMU_ATOMIC128_H
29
30
+#include "qemu/atomic.h"
31
#include "qemu/int128.h"
32
33
/*
34
--
35
2.43.0
36
37
diff view generated by jsdifflib
New patch
[PULL 22/23] accel/tcg: Build tcg-runtime.c once
1
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
accel/tcg/tcg-runtime.c | 8 ++------
5
accel/tcg/meson.build | 2 +-
6
2 files changed, 3 insertions(+), 7 deletions(-)
1
7
8
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/accel/tcg/tcg-runtime.c
11
+++ b/accel/tcg/tcg-runtime.c
12
@@ -XXX,XX +XXX,XX @@
13
*/
14
#include "qemu/osdep.h"
15
#include "qemu/host-utils.h"
16
-#include "cpu.h"
17
+#include "exec/cpu-common.h"
18
#include "exec/helper-proto-common.h"
19
-#include "exec/cpu_ldst.h"
20
-#include "exec/exec-all.h"
21
-#include "disas/disas.h"
22
-#include "exec/log.h"
23
-#include "tcg/tcg.h"
24
+#include "accel/tcg/getpc.h"
25
26
#define HELPER_H "accel/tcg/tcg-runtime.h"
27
#include "exec/helper-info.c.inc"
28
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
29
index XXXXXXX..XXXXXXX 100644
30
--- a/accel/tcg/meson.build
31
+++ b/accel/tcg/meson.build
32
@@ -XXX,XX +XXX,XX @@
33
common_ss.add(when: 'CONFIG_TCG', if_true: files(
34
'cpu-exec-common.c',
35
+ 'tcg-runtime.c',
36
))
37
tcg_specific_ss = ss.source_set()
38
tcg_specific_ss.add(files(
39
@@ -XXX,XX +XXX,XX @@ tcg_specific_ss.add(files(
40
'cpu-exec.c',
41
'tb-maint.c',
42
'tcg-runtime-gvec.c',
43
- 'tcg-runtime.c',
44
'translate-all.c',
45
'translator.c',
46
))
47
--
48
2.43.0
diff view generated by jsdifflib
New patch
[PULL 23/23] accel/tcg: Build tcg-runtime-gvec.c once
1
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
accel/tcg/tcg-runtime-gvec.c | 1 -
7
accel/tcg/meson.build | 2 +-
8
2 files changed, 1 insertion(+), 2 deletions(-)
1
9
10
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/accel/tcg/tcg-runtime-gvec.c
13
+++ b/accel/tcg/tcg-runtime-gvec.c
14
@@ -XXX,XX +XXX,XX @@
15
16
#include "qemu/osdep.h"
17
#include "qemu/host-utils.h"
18
-#include "cpu.h"
19
#include "exec/helper-proto-common.h"
20
#include "tcg/tcg-gvec-desc.h"
21
22
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
23
index XXXXXXX..XXXXXXX 100644
24
--- a/accel/tcg/meson.build
25
+++ b/accel/tcg/meson.build
26
@@ -XXX,XX +XXX,XX @@
27
common_ss.add(when: 'CONFIG_TCG', if_true: files(
28
'cpu-exec-common.c',
29
'tcg-runtime.c',
30
+ 'tcg-runtime-gvec.c',
31
))
32
tcg_specific_ss = ss.source_set()
33
tcg_specific_ss.add(files(
34
'tcg-all.c',
35
'cpu-exec.c',
36
'tb-maint.c',
37
- 'tcg-runtime-gvec.c',
38
'translate-all.c',
39
'translator.c',
40
))
41
--
42
2.43.0
43
44
diff view generated by jsdifflib
New patch
[PATCH v2] linux-user/riscv: Fix handling of cpu mask in riscv_hwprobe syscall
1
The third argument of the syscall contains the size of the
2
cpu mask in bytes, not bits. Nor is the size rounded up to
3
a multiple of sizeof(abi_ulong).
1
4
5
Cc: qemu-stable@nongnu.org
6
Reported-by: Andreas Schwab <schwab@suse.de>
7
Fixes: 9e1c7d982d7 ("linux-user/riscv: Add syscall riscv_hwprobe")
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
10
linux-user/syscall.c | 55 +++++++++++++++++++++++---------------------
11
1 file changed, 29 insertions(+), 26 deletions(-)
12
13
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/linux-user/syscall.c
16
+++ b/linux-user/syscall.c
17
@@ -XXX,XX +XXX,XX @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
18
}
19
}
20
21
-static int cpu_set_valid(abi_long arg3, abi_long arg4)
22
+/*
23
+ * If the cpumask_t of (target_cpus, cpusetsize) cannot be read: -EFAULT.
24
+ * If the cpumast_t has no bits set: -EINVAL.
25
+ * Otherwise the cpumask_t contains some bit set: 0.
26
+ * Unlike the kernel, we do not mask cpumask_t by the set of online cpus,
27
+ * nor bound the search by cpumask_size().
28
+ */
29
+static int nonempty_cpu_set(abi_ulong cpusetsize, abi_ptr target_cpus)
30
{
31
- int ret, i, tmp;
32
- size_t host_mask_size, target_mask_size;
33
- unsigned long *host_mask;
34
+ unsigned char *p = lock_user(VERIFY_READ, target_cpus, cpusetsize, 1);
35
+ int ret = -TARGET_EFAULT;
36
37
- /*
38
- * cpu_set_t represent CPU masks as bit masks of type unsigned long *.
39
- * arg3 contains the cpu count.
40
- */
41
- tmp = (8 * sizeof(abi_ulong));
42
- target_mask_size = ((arg3 + tmp - 1) / tmp) * sizeof(abi_ulong);
43
- host_mask_size = (target_mask_size + (sizeof(*host_mask) - 1)) &
44
- ~(sizeof(*host_mask) - 1);
45
-
46
- host_mask = alloca(host_mask_size);
47
-
48
- ret = target_to_host_cpu_mask(host_mask, host_mask_size,
49
- arg4, target_mask_size);
50
- if (ret != 0) {
51
- return ret;
52
- }
53
-
54
- for (i = 0 ; i < host_mask_size / sizeof(*host_mask); i++) {
55
- if (host_mask[i] != 0) {
56
- return 0;
57
+ if (p) {
58
+ ret = -TARGET_EINVAL;
59
+ /*
60
+ * Since we only care about the empty/non-empty state of the cpumask_t
61
+ * not the individual bits, we do not need to repartition the bits
62
+ * from target abi_ulong to host unsigned long.
63
+ *
64
+ * Note that the kernel does not round up cpusetsize to a multiple of
65
+ * sizeof(abi_ulong). After bounding cpusetsize by cpumask_size(),
66
+ * it copies exactly cpusetsize bytes into a zeroed buffer.
67
+ */
68
+ for (abi_ulong i = 0; i < cpusetsize; ++i) {
69
+ if (p[i]) {
70
+ ret = 0;
71
+ break;
72
+ }
73
}
74
+ unlock_user(p, target_cpus, 0);
75
}
76
- return -TARGET_EINVAL;
77
+ return ret;
78
}
79
80
static abi_long do_riscv_hwprobe(CPUArchState *cpu_env, abi_long arg1,
81
@@ -XXX,XX +XXX,XX @@ static abi_long do_riscv_hwprobe(CPUArchState *cpu_env, abi_long arg1,
82
83
/* check cpu_set */
84
if (arg3 != 0) {
85
- ret = cpu_set_valid(arg3, arg4);
86
+ ret = nonempty_cpu_set(arg3, arg4);
87
if (ret != 0) {
88
return ret;
89
}
90
--
91
2.43.0
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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