[PULL v2.5 00/27] tcg patch queue
[PULL v2 00/10] tcg patch queue
1
v2: Fix target/loongarch printf formats for vaddr
1
V2 replaces the tcg const temp overflow patch.
2
Include two more reviewed patches.
3
2
4
This time with actual pull urls. :-/
5
3
6
r~
4
r~
7
5
8
6
9
The following changes since commit db7aa99ef894e88fc5eedf02ca2579b8c344b2ec:
7
The following changes since commit 0e32462630687a18039464511bd0447ada5709c3:
10
8
11
Merge tag 'hw-misc-20250216' of https://github.com/philmd/qemu into staging (2025-02-16 20:48:06 -0500)
9
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-6.0-pull-request' into staging (2021-01-22 10:35:55 +0000)
12
10
13
are available in the Git repository at:
11
are available in the Git repository at:
14
12
15
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215-2
13
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210124
16
14
17
for you to fetch changes up to a39bdd0f4ba96fcbb6b5bcb6e89591d2b24f52eb:
15
for you to fetch changes up to ae30e86661b0f48562cd95918d37cbeec5d02262:
18
16
19
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 (2025-02-17 09:52:07 -0800)
17
tcg: Restart code generation when we run out of temps (2021-01-24 08:03:27 -1000)
20
18
21
----------------------------------------------------------------
19
----------------------------------------------------------------
22
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
20
Fix tcg constant temp overflow.
23
tcg: Cleanups after disallowing 64-on-32
21
Fix running during atomic single-step.
24
tcg: Introduce constraint for zero register
22
Partial support for apple silicon.
25
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
23
Cleanups for accel/tcg.
26
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
27
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
28
linux-user: Fix alignment when unmapping excess reservation
29
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
30
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
31
target/sparc: fake UltraSPARC T1 PCR and PIC registers
32
24
33
----------------------------------------------------------------
25
----------------------------------------------------------------
34
Andreas Schwab (1):
26
Douglas Crosher (1):
35
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
27
tcg: update the cpu running flag in cpu_exec_step_atomic
36
28
37
Artyom Tarasenko (1):
29
Philippe Mathieu-Daudé (4):
38
target/sparc: fake UltraSPARC T1 PCR and PIC registers
30
accel/tcg: Make cpu_gen_init() static
31
accel/tcg: Restrict tb_gen_code() from other accelerators
32
accel/tcg: Declare missing cpu_loop_exit*() stubs
33
accel/tcg: Restrict cpu_io_recompile() from other accelerators
39
34
40
Fabiano Rosas (1):
35
Richard Henderson (4):
41
elfload: Fix alignment when unmapping excess reservation
36
qemu/compiler: Split out qemu_build_not_reached_always
37
tcg: Optimize inline dup_const for MO_64
38
accel/tcg: Move tb_flush_jmp_cache() to cputlb.c
39
tcg: Restart code generation when we run out of temps
42
40
43
Mikael Szreder (2):
41
Roman Bolshakov (1):
44
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
42
tcg: Toggle page execution for Apple Silicon
45
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
46
43
47
Richard Henderson (22):
44
accel/tcg/internal.h | 20 ++++++++++++++++++++
48
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
45
include/exec/exec-all.h | 11 -----------
49
tcg: Remove TCG_OVERSIZED_GUEST
46
include/qemu/compiler.h | 5 +++--
50
tcg: Drop support for two address registers in gen_ldst
47
include/qemu/osdep.h | 28 ++++++++++++++++++++++++++++
51
tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
48
include/tcg/tcg.h | 6 +++++-
52
tcg/arm: Drop addrhi from prepare_host_addr
49
accel/stubs/tcg-stub.c | 10 ++++++++++
53
tcg/i386: Drop addrhi from prepare_host_addr
50
accel/tcg/cpu-exec.c | 7 +++++++
54
tcg/mips: Drop addrhi from prepare_host_addr
51
accel/tcg/cputlb.c | 19 +++++++++++++++++++
55
tcg/ppc: Drop addrhi from prepare_host_addr
52
accel/tcg/translate-all.c | 38 +++++++++++++++++++-------------------
56
tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
53
tcg/tcg.c | 12 +++++++++---
57
plugins: Fix qemu_plugin_read_memory_vaddr parameters
54
10 files changed, 120 insertions(+), 36 deletions(-)
58
accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
55
create mode 100644 accel/tcg/internal.h
59
target/loongarch: Use VADDR_PRIx for logging pc_next
60
include/exec: Change vaddr to uintptr_t
61
include/exec: Use uintptr_t in CPUTLBEntry
62
tcg: Introduce the 'z' constraint for a hardware zero register
63
tcg/aarch64: Use 'z' constraint
64
tcg/loongarch64: Use 'z' constraint
65
tcg/mips: Use 'z' constraint
66
tcg/riscv: Use 'z' constraint
67
tcg/sparc64: Use 'z' constraint
68
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
69
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
70
56
71
include/exec/tlb-common.h | 10 +-
72
include/exec/vaddr.h | 16 +-
73
include/qemu/atomic.h | 18 +-
74
include/tcg/oversized-guest.h | 23 ---
75
include/tcg/tcg-opc.h | 28 +--
76
include/tcg/tcg.h | 3 +-
77
linux-user/aarch64/target_signal.h | 2 +
78
linux-user/arm/target_signal.h | 2 +
79
linux-user/generic/signal.h | 1 -
80
linux-user/i386/target_signal.h | 2 +
81
linux-user/m68k/target_signal.h | 1 +
82
linux-user/microblaze/target_signal.h | 2 +
83
linux-user/ppc/target_signal.h | 2 +
84
linux-user/s390x/target_signal.h | 2 +
85
linux-user/sh4/target_signal.h | 2 +
86
linux-user/x86_64/target_signal.h | 2 +
87
linux-user/xtensa/target_signal.h | 2 +
88
tcg/aarch64/tcg-target-con-set.h | 12 +-
89
tcg/aarch64/tcg-target.h | 2 +
90
tcg/loongarch64/tcg-target-con-set.h | 15 +-
91
tcg/loongarch64/tcg-target-con-str.h | 1 -
92
tcg/loongarch64/tcg-target-has.h | 2 -
93
tcg/loongarch64/tcg-target.h | 2 +
94
tcg/mips/tcg-target-con-set.h | 26 +--
95
tcg/mips/tcg-target-con-str.h | 1 -
96
tcg/mips/tcg-target.h | 2 +
97
tcg/riscv/tcg-target-con-set.h | 10 +-
98
tcg/riscv/tcg-target-con-str.h | 1 -
99
tcg/riscv/tcg-target-has.h | 2 -
100
tcg/riscv/tcg-target.h | 2 +
101
tcg/sparc64/tcg-target-con-set.h | 12 +-
102
tcg/sparc64/tcg-target-con-str.h | 1 -
103
tcg/sparc64/tcg-target.h | 3 +-
104
tcg/tci/tcg-target.h | 1 -
105
accel/tcg/cputlb.c | 32 +---
106
accel/tcg/tcg-all.c | 9 +-
107
linux-user/elfload.c | 4 +-
108
plugins/api.c | 2 +-
109
target/arm/ptw.c | 34 ----
110
target/loongarch/tcg/translate.c | 2 +-
111
target/riscv/cpu_helper.c | 13 +-
112
target/sparc/gdbstub.c | 18 +-
113
target/sparc/translate.c | 19 +++
114
tcg/optimize.c | 21 +--
115
tcg/tcg-op-ldst.c | 103 +++--------
116
tcg/tcg.c | 97 +++++------
117
tcg/tci.c | 119 +++----------
118
docs/devel/multi-thread-tcg.rst | 1 -
119
docs/devel/tcg-ops.rst | 4 +-
120
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
121
target/sparc/insns.decode | 19 ++-
122
tcg/aarch64/tcg-target.c.inc | 86 ++++------
123
tcg/arm/tcg-target.c.inc | 114 ++++---------
124
tcg/i386/tcg-target.c.inc | 190 +++++----------------
125
tcg/loongarch64/tcg-target.c.inc | 72 +++-----
126
tcg/mips/tcg-target.c.inc | 169 ++++++------------
127
tcg/ppc/tcg-target.c.inc | 164 +++++-------------
128
tcg/riscv/tcg-target.c.inc | 56 +++---
129
tcg/s390x/tcg-target.c.inc | 40 ++---
130
tcg/sparc64/tcg-target.c.inc | 45 ++---
131
tcg/tci/tcg-target.c.inc | 60 ++-----
132
61 files changed, 548 insertions(+), 1160 deletions(-)
133
delete mode 100644 include/tcg/oversized-guest.h
diff view generated by jsdifflib
New patch
[PULL v2 10/10] tcg: Restart code generation when we run out of temps
1
Some large translation blocks can generate so many unique
2
constants that we run out of temps to hold them. In this
3
case, longjmp back to the start of code generation and
4
restart with a smaller translation block.
1
5
6
Buglink: https://bugs.launchpad.net/bugs/1912065
7
Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
include/tcg/tcg.h | 3 +++
12
accel/tcg/translate-all.c | 15 ++++++++++++++-
13
tcg/tcg.c | 11 ++++++++---
14
3 files changed, 25 insertions(+), 4 deletions(-)
15
16
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/tcg/tcg.h
19
+++ b/include/tcg/tcg.h
20
@@ -XXX,XX +XXX,XX @@ struct TCGContext {
21
22
uint16_t gen_insn_end_off[TCG_MAX_INSNS];
23
target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
24
+
25
+ /* Exit to translator on overflow. */
26
+ sigjmp_buf jmp_trans;
27
};
28
29
static inline bool temp_readonly(TCGTemp *ts)
30
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/accel/tcg/translate-all.c
33
+++ b/accel/tcg/translate-all.c
34
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
35
ti = profile_getclock();
36
#endif
37
38
+ gen_code_size = sigsetjmp(tcg_ctx->jmp_trans, 0);
39
+ if (unlikely(gen_code_size != 0)) {
40
+ goto error_return;
41
+ }
42
+
43
tcg_func_start(tcg_ctx);
44
45
tcg_ctx->cpu = env_cpu(env);
46
gen_intermediate_code(cpu, tb, max_insns);
47
tcg_ctx->cpu = NULL;
48
+ max_insns = tb->icount;
49
50
trace_translate_block(tb, tb->pc, tb->tc.ptr);
51
52
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
53
54
gen_code_size = tcg_gen_code(tcg_ctx, tb);
55
if (unlikely(gen_code_size < 0)) {
56
+ error_return:
57
switch (gen_code_size) {
58
case -1:
59
/*
60
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
61
* flush the TBs, allocate a new TB, re-initialize it per
62
* above, and re-do the actual code generation.
63
*/
64
+ qemu_log_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT,
65
+ "Restarting code generation for "
66
+ "code_gen_buffer overflow\n");
67
goto buffer_overflow;
68
69
case -2:
70
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
71
* Try again with half as many insns as we attempted this time.
72
* If a single insn overflows, there's a bug somewhere...
73
*/
74
- max_insns = tb->icount;
75
assert(max_insns > 1);
76
max_insns /= 2;
77
+ qemu_log_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT,
78
+ "Restarting code generation with "
79
+ "smaller translation block (max %d insns)\n",
80
+ max_insns);
81
goto tb_overflow;
82
83
default:
84
diff --git a/tcg/tcg.c b/tcg/tcg.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/tcg/tcg.c
87
+++ b/tcg/tcg.c
88
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
89
QSIMPLEQ_INIT(&s->labels);
90
}
91
92
-static inline TCGTemp *tcg_temp_alloc(TCGContext *s)
93
+static TCGTemp *tcg_temp_alloc(TCGContext *s)
94
{
95
int n = s->nb_temps++;
96
- tcg_debug_assert(n < TCG_MAX_TEMPS);
97
+
98
+ if (n >= TCG_MAX_TEMPS) {
99
+ /* Signal overflow, starting over with fewer guest insns. */
100
+ siglongjmp(s->jmp_trans, -2);
101
+ }
102
return memset(&s->temps[n], 0, sizeof(TCGTemp));
103
}
104
105
-static inline TCGTemp *tcg_global_alloc(TCGContext *s)
106
+static TCGTemp *tcg_global_alloc(TCGContext *s)
107
{
108
TCGTemp *ts;
109
110
tcg_debug_assert(s->nb_globals == s->nb_temps);
111
+ tcg_debug_assert(s->nb_globals < TCG_MAX_TEMPS);
112
s->nb_globals++;
113
ts = tcg_temp_alloc(s);
114
ts->kind = TEMP_GLOBAL;
115
--
116
2.25.1
117
118
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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