On 2/17/25 04:50, Peter Maydell wrote:
> Currently we have a compile-time shortcut where we return a hardcode
> value from snan_bit_is_one() on everything except MIPS, because we
> know that's the only target that needs to change
> status->no_signaling_nans at runtime.
Pasto from the previous patch on the variable name.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
>
> Remove the ifdef, so we always look at the status flag. This means
> we must update the two targets (HPPA and SH4) that were previously
> hardcoded to return true so that they set the status flag correctly.
>
> This has no behavioural change, but will be necessary if we want to
> build softfloat once for all targets.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/hppa/fpu_helper.c | 1 +
> target/sh4/cpu.c | 1 +
> fpu/softfloat-specialize.c.inc | 7 -------
> 3 files changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
> index 8ff4b448049..a62d9d30831 100644
> --- a/target/hppa/fpu_helper.c
> +++ b/target/hppa/fpu_helper.c
> @@ -67,6 +67,7 @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
> set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
> /* Default NaN: sign bit clear, msb-1 frac bit set */
> set_float_default_nan_pattern(0b00100000, &env->fp_status);
> + set_snan_bit_is_one(true, &env->fp_status);
> /*
> * "PA-RISC 2.0 Architecture" says it is IMPDEF whether the flushing
> * enabled by FPSR.D happens before or after rounding. We pick "before"
> diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
> index 4ac693d99bd..ccfe222bdf3 100644
> --- a/target/sh4/cpu.c
> +++ b/target/sh4/cpu.c
> @@ -128,6 +128,7 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
> set_flush_to_zero(1, &env->fp_status);
> #endif
> set_default_nan_mode(1, &env->fp_status);
> + set_snan_bit_is_one(true, &env->fp_status);
> /* sign bit clear, set all frac bits other than msb */
> set_float_default_nan_pattern(0b00111111, &env->fp_status);
> /*
> diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
> index a2c6afad5da..ba4fa08b7be 100644
> --- a/fpu/softfloat-specialize.c.inc
> +++ b/fpu/softfloat-specialize.c.inc
> @@ -93,17 +93,10 @@ static inline bool no_signaling_nans(float_status *status)
> * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
> * the msb must be zero. MIPS is (so far) unique in supporting both the
> * 2008 revision and backward compatibility with their original choice.
> - * Thus for MIPS we must make the choice at runtime.
> */
> static inline bool snan_bit_is_one(float_status *status)
> {
> -#if defined(TARGET_MIPS)
> return status->snan_bit_is_one;
> -#elif defined(TARGET_HPPA) || defined(TARGET_SH4)
> - return 1;
> -#else
> - return 0;
> -#endif
> }
>
> /*----------------------------------------------------------------------------