The instruction set does not implement nor with immediate.
There is no reason to pretend that we do.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index e061ba1654..72e068255c 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1413,12 +1413,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
case INDEX_op_nor_i32:
case INDEX_op_nor_i64:
- if (c2) {
- tcg_out_opc_ori(s, a0, a1, a2);
- tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO);
- } else {
- tcg_out_opc_nor(s, a0, a1, a2);
- }
+ tcg_out_opc_nor(s, a0, a1, a2);
break;
case INDEX_op_extract_i32:
@@ -2308,8 +2303,7 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_nor_i32:
case INDEX_op_nor_i64:
- /* LoongArch reg-imm bitops have their imms ZERO-extended */
- return C_O1_I2(r, r, rU);
+ return C_O1_I2(r, r, r);
case INDEX_op_clz_i32:
case INDEX_op_clz_i64:
--
2.43.0