hw/misc/mchp_pfsoc_sysreg.c | 7 ++ hw/riscv/microchip_pfsoc.c | 147 +++++++++++++++++++++-------- include/hw/riscv/microchip_pfsoc.h | 1 + 3 files changed, 115 insertions(+), 40 deletions(-)
Booting the microchip-icicle-kit machine using the latest PolarFire SoC Hart Software Services (HSS) no longer works since Qemu lacks support for several registers (clocks, DRAM controller). Also reading from the SDCard does not work currently. In order to allow tests runs for real-time kernels such as RTEMS and Zephyr, improve the boot customization. This patch set enables a direct run of kernel executables, for example: qemu-system-riscv64 -no-reboot -nographic \ -serial null -serial mon:stdio \ -smp 2 \ -bios none \ -machine microchip-icicle-kit,clint-timebase-frequency=10000000 \ -kernel rtos.elf Sebastian Huber (5): hw/misc: Add MPFS system reset support hw/riscv: More flexible FDT placement for MPFS hw/riscv: Make FDT optional for MPFS hw/riscv: Allow direct start of kernel for MPFS hw/riscv: Configurable MPFS CLINT timebase freq hw/misc/mchp_pfsoc_sysreg.c | 7 ++ hw/riscv/microchip_pfsoc.c | 147 +++++++++++++++++++++-------- include/hw/riscv/microchip_pfsoc.h | 1 + 3 files changed, 115 insertions(+), 40 deletions(-) -- 2.43.0
+cc qemu-riscv, Alistar.
On Fri, Feb 14, 2025 at 07:24:37AM +0100, Sebastian Huber wrote:
> Booting the microchip-icicle-kit machine using the latest PolarFire SoC
> Hart Software Services (HSS) no longer works since Qemu lacks support
> for several registers (clocks, DRAM controller). Also reading from the
> SDCard does not work currently.
On that note, I think the inaccurate docs about polarfire should be
removed. There's a wiki page here with dead links, or links to things
that do not work anymore:
https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit
I think the whole section should be removed, find it kinda odd that
there's a polarfire section but not for any other board. Either way,
it's talking about something that just does not work, the current HSS
and Yocto don't boot.
There's also a docs page here:
https://www.qemu.org/docs/master/system/riscv/microchip-icicle-kit.html
that has a copy of the table your patch 4 modifies, that probably should
be updated to match your changes.
In a similar vein to the wiki, it talks about the HSS and booting a
yocto wic image. I think those should be deleted since they don't work.
Alistar/Other RISC-V folks, what do you think? Bin wrote the port but
seems to be AFK and I don't have the capacity to fix any of that stuff
on top of what I already do in my spare time - do you agree that
deleting the now inaccurate docs makes sense?
> In order to allow tests runs for real-time kernels such as RTEMS and
> Zephyr, improve the boot customization. This patch set enables a direct
> run of kernel executables, for example:
>
> qemu-system-riscv64 -no-reboot -nographic \
> -serial null -serial mon:stdio \
> -smp 2 \
> -bios none \
> -machine microchip-icicle-kit,clint-timebase-frequency=10000000 \
> -kernel rtos.elf
The series breaks my usage:
qemu//build/qemu-system-riscv64 -M microchip-icicle-kit \
-m 3G -smp 5 \
-kernel vmlinux.bin \
-dtb riscvpc.dtb \
-initrd initramfs.cpio.gz \
-display none -serial null \
-serial mon:stdio \
-D qemu.log -d unimp
opensbi-riscv64-generic-fw_dynamic.bin: No such file or directory
qemu-system-riscv64: could not load firmware 'opensbi-riscv64-generic-fw_dynamic.bin'
make: *** [Makefile:305: qemu-icicle] Error 1
Figure it is likely to be your patch 4? The file does exist, so probably
some sort of path-to-it issues?
Cheers,
Conor.
>
> Sebastian Huber (5):
> hw/misc: Add MPFS system reset support
> hw/riscv: More flexible FDT placement for MPFS
> hw/riscv: Make FDT optional for MPFS
> hw/riscv: Allow direct start of kernel for MPFS
> hw/riscv: Configurable MPFS CLINT timebase freq
>
> hw/misc/mchp_pfsoc_sysreg.c | 7 ++
> hw/riscv/microchip_pfsoc.c | 147 +++++++++++++++++++++--------
> include/hw/riscv/microchip_pfsoc.h | 1 +
> 3 files changed, 115 insertions(+), 40 deletions(-)
>
> --
> 2.43.0
>
>
On Fri, Feb 21, 2025 at 4:31 AM Conor Dooley <conor@kernel.org> wrote: > > +cc qemu-riscv, Alistar. > > On Fri, Feb 14, 2025 at 07:24:37AM +0100, Sebastian Huber wrote: > > Booting the microchip-icicle-kit machine using the latest PolarFire SoC > > Hart Software Services (HSS) no longer works since Qemu lacks support > > for several registers (clocks, DRAM controller). Also reading from the > > SDCard does not work currently. > > On that note, I think the inaccurate docs about polarfire should be > removed. There's a wiki page here with dead links, or links to things > that do not work anymore: > https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit > I think the whole section should be removed, find it kinda odd that > there's a polarfire section but not for any other board. Either way, > it's talking about something that just does not work, the current HSS > and Yocto don't boot. The wiki is independent of the QEMU code base, so you can modify it. I agree that we should remove outdated/wrong information as it's very confusing to users. > > There's also a docs page here: > https://www.qemu.org/docs/master/system/riscv/microchip-icicle-kit.html That is generated from the QEMU codebase `docs/system/riscv/microchip-icicle-kit.rst` and should be updated, ideally with this patch set > that has a copy of the table your patch 4 modifies, that probably should > be updated to match your changes. > > In a similar vein to the wiki, it talks about the HSS and booting a > yocto wic image. I think those should be deleted since they don't work. Agreed Alistair > > Alistar/Other RISC-V folks, what do you think? Bin wrote the port but > seems to be AFK and I don't have the capacity to fix any of that stuff > on top of what I already do in my spare time - do you agree that > deleting the now inaccurate docs makes sense? > > > In order to allow tests runs for real-time kernels such as RTEMS and > > Zephyr, improve the boot customization. This patch set enables a direct > > run of kernel executables, for example: > > > > qemu-system-riscv64 -no-reboot -nographic \ > > -serial null -serial mon:stdio \ > > -smp 2 \ > > -bios none \ > > -machine microchip-icicle-kit,clint-timebase-frequency=10000000 \ > > -kernel rtos.elf > > The series breaks my usage: > qemu//build/qemu-system-riscv64 -M microchip-icicle-kit \ > -m 3G -smp 5 \ > -kernel vmlinux.bin \ > -dtb riscvpc.dtb \ > -initrd initramfs.cpio.gz \ > -display none -serial null \ > -serial mon:stdio \ > -D qemu.log -d unimp > opensbi-riscv64-generic-fw_dynamic.bin: No such file or directory > qemu-system-riscv64: could not load firmware 'opensbi-riscv64-generic-fw_dynamic.bin' > make: *** [Makefile:305: qemu-icicle] Error 1 > > Figure it is likely to be your patch 4? The file does exist, so probably > some sort of path-to-it issues? > > Cheers, > Conor. > > > > > Sebastian Huber (5): > > hw/misc: Add MPFS system reset support > > hw/riscv: More flexible FDT placement for MPFS > > hw/riscv: Make FDT optional for MPFS > > hw/riscv: Allow direct start of kernel for MPFS > > hw/riscv: Configurable MPFS CLINT timebase freq > > > > hw/misc/mchp_pfsoc_sysreg.c | 7 ++ > > hw/riscv/microchip_pfsoc.c | 147 +++++++++++++++++++++-------- > > include/hw/riscv/microchip_pfsoc.h | 1 + > > 3 files changed, 115 insertions(+), 40 deletions(-) > > > > -- > > 2.43.0 > > > >
On Mon, Feb 24, 2025 at 03:14:00PM +1000, Alistair Francis wrote: > On Fri, Feb 21, 2025 at 4:31 AM Conor Dooley <conor@kernel.org> wrote: > > > > +cc qemu-riscv, Alistar. > > > > On Fri, Feb 14, 2025 at 07:24:37AM +0100, Sebastian Huber wrote: > > > Booting the microchip-icicle-kit machine using the latest PolarFire SoC > > > Hart Software Services (HSS) no longer works since Qemu lacks support > > > for several registers (clocks, DRAM controller). Also reading from the > > > SDCard does not work currently. > > > > On that note, I think the inaccurate docs about polarfire should be > > removed. There's a wiki page here with dead links, or links to things > > that do not work anymore: > > https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit > > I think the whole section should be removed, find it kinda odd that > > there's a polarfire section but not for any other board. Either way, > > it's talking about something that just does not work, the current HSS > > and Yocto don't boot. > > The wiki is independent of the QEMU code base, so you can modify it. I > agree that we should remove outdated/wrong information as it's very > confusing to users. I don't have an account to make the modification, any clue who has one and can hook me up with one? > > There's also a docs page here: > > https://www.qemu.org/docs/master/system/riscv/microchip-icicle-kit.html > > That is generated from the QEMU codebase > `docs/system/riscv/microchip-icicle-kit.rst` and should be updated, > ideally with this patch set Ye, I think so too. > > that has a copy of the table your patch 4 modifies, that probably should > > be updated to match your changes. > > > > In a similar vein to the wiki, it talks about the HSS and booting a > > yocto wic image. I think those should be deleted since they don't work.
On Tue, Feb 25, 2025 at 7:28 AM Conor Dooley <conor@kernel.org> wrote: > > On Mon, Feb 24, 2025 at 03:14:00PM +1000, Alistair Francis wrote: > > On Fri, Feb 21, 2025 at 4:31 AM Conor Dooley <conor@kernel.org> wrote: > > > > > > +cc qemu-riscv, Alistar. > > > > > > On Fri, Feb 14, 2025 at 07:24:37AM +0100, Sebastian Huber wrote: > > > > Booting the microchip-icicle-kit machine using the latest PolarFire SoC > > > > Hart Software Services (HSS) no longer works since Qemu lacks support > > > > for several registers (clocks, DRAM controller). Also reading from the > > > > SDCard does not work currently. > > > > > > On that note, I think the inaccurate docs about polarfire should be > > > removed. There's a wiki page here with dead links, or links to things > > > that do not work anymore: > > > https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit > > > I think the whole section should be removed, find it kinda odd that > > > there's a polarfire section but not for any other board. Either way, > > > it's talking about something that just does not work, the current HSS > > > and Yocto don't boot. > > > > The wiki is independent of the QEMU code base, so you can modify it. I > > agree that we should remove outdated/wrong information as it's very > > confusing to users. > > I don't have an account to make the modification, any clue who has one > and can hook me up with one? @Peter Maydell @Philippe Mathieu-Daudé can you create wiki accounts? I don't seem to have permissions to create new accounts Alistair
Hi Conor, On 20/2/25 19:30, Conor Dooley wrote: > +cc qemu-riscv, Alistar. > > On Fri, Feb 14, 2025 at 07:24:37AM +0100, Sebastian Huber wrote: >> Booting the microchip-icicle-kit machine using the latest PolarFire SoC >> Hart Software Services (HSS) no longer works since Qemu lacks support >> for several registers (clocks, DRAM controller). Also reading from the >> SDCard does not work currently. > > On that note, I think the inaccurate docs about polarfire should be > removed. There's a wiki page here with dead links, or links to things > that do not work anymore: > https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit > I think the whole section should be removed, find it kinda odd that > there's a polarfire section but not for any other board. Either way, > it's talking about something that just does not work, the current HSS > and Yocto don't boot. > > There's also a docs page here: > https://www.qemu.org/docs/master/system/riscv/microchip-icicle-kit.html > that has a copy of the table your patch 4 modifies, that probably should > be updated to match your changes. > > In a similar vein to the wiki, it talks about the HSS and booting a > yocto wic image. I think those should be deleted since they don't work. > > Alistar/Other RISC-V folks, what do you think? Bin wrote the port but > seems to be AFK and I don't have the capacity to fix any of that stuff > on top of what I already do in my spare time - do you agree that > deleting the now inaccurate docs makes sense? > >> In order to allow tests runs for real-time kernels such as RTEMS and >> Zephyr, improve the boot customization. This patch set enables a direct >> run of kernel executables, for example: >> >> qemu-system-riscv64 -no-reboot -nographic \ >> -serial null -serial mon:stdio \ >> -smp 2 \ >> -bios none \ >> -machine microchip-icicle-kit,clint-timebase-frequency=10000000 \ >> -kernel rtos.elf > > The series breaks my usage: > qemu//build/qemu-system-riscv64 -M microchip-icicle-kit \ > -m 3G -smp 5 \ > -kernel vmlinux.bin \ > -dtb riscvpc.dtb \ > -initrd initramfs.cpio.gz \ > -display none -serial null \ > -serial mon:stdio \ > -D qemu.log -d unimp > opensbi-riscv64-generic-fw_dynamic.bin: No such file or directory > qemu-system-riscv64: could not load firmware 'opensbi-riscv64-generic-fw_dynamic.bin' > make: *** [Makefile:305: qemu-icicle] Error 1 > > Figure it is likely to be your patch 4? The file does exist, so probably > some sort of path-to-it issues? Maybe missing the -L option? -L path set the directory for the BIOS, VGA BIOS and keymaps Regards, Phil.
----- Am 20. Feb 2025 um 23:29 schrieb Philippe Mathieu-Daudé philmd@linaro.org: > Hi Conor, > > On 20/2/25 19:30, Conor Dooley wrote: >> +cc qemu-riscv, Alistar. >> >> On Fri, Feb 14, 2025 at 07:24:37AM +0100, Sebastian Huber wrote: >>> Booting the microchip-icicle-kit machine using the latest PolarFire SoC >>> Hart Software Services (HSS) no longer works since Qemu lacks support >>> for several registers (clocks, DRAM controller). Also reading from the >>> SDCard does not work currently. >> >> On that note, I think the inaccurate docs about polarfire should be >> removed. There's a wiki page here with dead links, or links to things >> that do not work anymore: >> https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit >> I think the whole section should be removed, find it kinda odd that >> there's a polarfire section but not for any other board. Either way, >> it's talking about something that just does not work, the current HSS >> and Yocto don't boot. >> >> There's also a docs page here: >> https://www.qemu.org/docs/master/system/riscv/microchip-icicle-kit.html >> that has a copy of the table your patch 4 modifies, that probably should >> be updated to match your changes. >> >> In a similar vein to the wiki, it talks about the HSS and booting a >> yocto wic image. I think those should be deleted since they don't work. >> >> Alistar/Other RISC-V folks, what do you think? Bin wrote the port but >> seems to be AFK and I don't have the capacity to fix any of that stuff >> on top of what I already do in my spare time - do you agree that >> deleting the now inaccurate docs makes sense? >> >>> In order to allow tests runs for real-time kernels such as RTEMS and >>> Zephyr, improve the boot customization. This patch set enables a direct >>> run of kernel executables, for example: >>> >>> qemu-system-riscv64 -no-reboot -nographic \ >>> -serial null -serial mon:stdio \ >>> -smp 2 \ >>> -bios none \ >>> -machine microchip-icicle-kit,clint-timebase-frequency=10000000 \ >>> -kernel rtos.elf >> >> The series breaks my usage: >> qemu//build/qemu-system-riscv64 -M microchip-icicle-kit \ >> -m 3G -smp 5 \ >> -kernel vmlinux.bin \ >> -dtb riscvpc.dtb \ >> -initrd initramfs.cpio.gz \ >> -display none -serial null \ >> -serial mon:stdio \ >> -D qemu.log -d unimp >> opensbi-riscv64-generic-fw_dynamic.bin: No such file or directory >> qemu-system-riscv64: could not load firmware >> 'opensbi-riscv64-generic-fw_dynamic.bin' >> make: *** [Makefile:305: qemu-icicle] Error 1 >> >> Figure it is likely to be your patch 4? The file does exist, so probably >> some sort of path-to-it issues? > > Maybe missing the -L option? > > -L path set the directory for the BIOS, VGA BIOS and keymaps It was an error in patch 4/5. I sent a v2 version of it. You have to find the firmware, before you can load it. -- embedded brains GmbH & Co. KG Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.huber@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/
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