On 2/13/25 04:35, Jamin Lin wrote:
> To support AST2700 A1, some registers of the INTC(CPU Die) support one input
> pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC
> controller code for better clarity and consistency in naming conventions.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> hw/arm/aspeed_ast27x0.c | 2 +-
> hw/intc/aspeed_intc.c | 31 +++++++++++++++++--------------
> include/hw/intc/aspeed_intc.h | 11 ++++++-----
> 3 files changed, 24 insertions(+), 20 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 4862b215c1..18e14a7914 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -520,7 +520,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> sc->memmap[ASPEED_DEV_INTC]);
>
> /* GICINT orgates -> INTC -> GIC */
> - for (i = 0; i < ic->num_ints; i++) {
> + for (i = 0; i < ic->num_inpins; i++) {
> qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
> qdev_get_gpio_in(DEVICE(&a->intc), i));
> sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
> diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
> index cc2426fbac..95b40e1935 100644
> --- a/hw/intc/aspeed_intc.c
> +++ b/hw/intc/aspeed_intc.c
> @@ -41,8 +41,9 @@ static void aspeed_intc_update(AspeedINTCState *s, int irq, int level)
> AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
> const char *name = object_get_typename(OBJECT(s));
>
> - if (irq >= aic->num_ints) {
> - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
> + if (irq >= aic->num_inpins) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Invalid input pin index: %d\n",
> __func__, irq);
> return;
> }
> @@ -54,7 +55,7 @@ static void aspeed_intc_update(AspeedINTCState *s, int irq, int level)
> /*
> * The address of GICINT128 to GICINT136 are from 0x1000 to 0x1804.
> * Utilize "address & 0x0f00" to get the irq and irq output pin index
> - * The value of irq should be 0 to num_ints.
> + * The value of irq should be 0 to num_inpins.
> * The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on.
> */
> static void aspeed_intc_set_irq(void *opaque, int irq, int level)
> @@ -67,8 +68,8 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)
> uint32_t enable;
> int i;
>
> - if (irq >= aic->num_ints) {
> - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
> + if (irq >= aic->num_inpins) {
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid input pin index: %d\n",
> __func__, irq);
> return;
> }
> @@ -128,8 +129,9 @@ static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset,
>
> irq = (offset & 0x0f00) >> 8;
>
> - if (irq >= aic->num_ints) {
> - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
> + if (irq >= aic->num_inpins) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Invalid input pin index: %d\n",
> __func__, irq);
> return;
> }
> @@ -184,8 +186,9 @@ static void aspeed_intc_status_handler(AspeedINTCState *s, hwaddr offset,
>
> irq = (offset & 0x0f00) >> 8;
>
> - if (irq >= aic->num_ints) {
> - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
> + if (irq >= aic->num_inpins) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Invalid input pin index: %d\n",
> __func__, irq);
> return;
> }
> @@ -309,8 +312,8 @@ static void aspeed_intc_instance_init(Object *obj)
> AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
> int i;
>
> - assert(aic->num_ints <= ASPEED_INTC_NR_INTS);
> - for (i = 0; i < aic->num_ints; i++) {
> + assert(aic->num_inpins <= ASPEED_INTC_MAX_INPINS);
> + for (i = 0; i < aic->num_inpins; i++) {
> object_initialize_child(obj, "intc-orgates[*]", &s->orgates[i],
> TYPE_OR_IRQ);
> object_property_set_int(OBJECT(&s->orgates[i]), "num-lines",
> @@ -345,9 +348,9 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
>
> memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem);
>
> - qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints);
> + qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_inpins);
>
> - for (i = 0; i < aic->num_ints; i++) {
> + for (i = 0; i < aic->num_inpins; i++) {
> if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) {
> return;
> }
> @@ -385,7 +388,7 @@ static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
>
> dc->desc = "ASPEED 2700 INTC Controller";
> aic->num_lines = 32;
> - aic->num_ints = 9;
> + aic->num_inpins = 9;
> aic->mem_size = 0x4000;
> aic->reg_size = 0x2000;
> }
> diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
> index 749d7c55be..5f0429c7f9 100644
> --- a/include/hw/intc/aspeed_intc.h
> +++ b/include/hw/intc/aspeed_intc.h
> @@ -18,6 +18,7 @@ OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
>
> #define ASPEED_INTC_NR_REGS (0x2000 >> 2)
> #define ASPEED_INTC_NR_INTS 9
> +#define ASPEED_INTC_MAX_INPINS 9
>
> struct AspeedINTCState {
> /*< private >*/
> @@ -28,19 +29,19 @@ struct AspeedINTCState {
> MemoryRegion iomem_container;
>
> uint32_t regs[ASPEED_INTC_NR_REGS];
> - OrIRQState orgates[ASPEED_INTC_NR_INTS];
> + OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
> qemu_irq output_pins[ASPEED_INTC_NR_INTS];
>
> - uint32_t enable[ASPEED_INTC_NR_INTS];
> - uint32_t mask[ASPEED_INTC_NR_INTS];
> - uint32_t pending[ASPEED_INTC_NR_INTS];
> + uint32_t enable[ASPEED_INTC_MAX_INPINS];
> + uint32_t mask[ASPEED_INTC_MAX_INPINS];
> + uint32_t pending[ASPEED_INTC_MAX_INPINS];
> };
>
> struct AspeedINTCClass {
> SysBusDeviceClass parent_class;
>
> uint32_t num_lines;
> - uint32_t num_ints;
> + uint32_t num_inpins;
> uint64_t mem_size;
> uint64_t reg_size;
> const MemoryRegionOps *reg_ops;