target/tricore: Inline TARGET_LONG_BITS in decode_rr_logical_shift()

[PATCH] target/tricore: Inline TARGET_LONG_BITS in decode_rr_logical_shift()

Posted by Philippe Mathieu-Daudé 1 month ago

We only support 32-bit TriCore architecture.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/tricore/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 6819b776686..c5b783b6a70 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -5936,7 +5936,7 @@ static void decode_rr_logical_shift(DisasContext *ctx)
         break;
     case OPC2_32_RR_CLO:
         tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
-        tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS);
+        tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32);
         break;
     case OPC2_32_RR_CLO_H:
         gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
@@ -5948,7 +5948,7 @@ static void decode_rr_logical_shift(DisasContext *ctx)
         gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
         break;
     case OPC2_32_RR_CLZ:
-        tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS);
+        tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32);
         break;
     case OPC2_32_RR_CLZ_H:
         gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
-- 
2.47.1

Re: [PATCH] target/tricore: Inline TARGET_LONG_BITS in decode_rr_logical_shift()

Posted by Bastian Koppelmann 1 month ago

On Thu, Feb 06, 2025 at 06:32:58PM +0100, Philippe Mathieu-Daudé wrote:
> We only support 32-bit TriCore architecture.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/tricore/translate.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

Cheers,
Bastian

Re: [PATCH] target/tricore: Inline TARGET_LONG_BITS in decode_rr_logical_shift()

Posted by Richard Henderson 1 month ago

On 2/6/25 09:32, Philippe Mathieu-Daudé wrote:
> We only support 32-bit TriCore architecture.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/tricore/translate.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> index 6819b776686..c5b783b6a70 100644
> --- a/target/tricore/translate.c
> +++ b/target/tricore/translate.c
> @@ -5936,7 +5936,7 @@ static void decode_rr_logical_shift(DisasContext *ctx)
>           break;
>       case OPC2_32_RR_CLO:
>           tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
> -        tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS);
> +        tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32);
>           break;
>       case OPC2_32_RR_CLO_H:
>           gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
> @@ -5948,7 +5948,7 @@ static void decode_rr_logical_shift(DisasContext *ctx)
>           gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
>           break;
>       case OPC2_32_RR_CLZ:
> -        tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS);
> +        tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32);
>           break;
>       case OPC2_32_RR_CLZ_H:
>           gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);

Leave it alone unless you swap /_tl/_i32/ ?


r~

Re: [PATCH] target/tricore: Inline TARGET_LONG_BITS in decode_rr_logical_shift()

Posted by Philippe Mathieu-Daudé 1 month ago

On 6/2/25 18:47, Richard Henderson wrote:
> On 2/6/25 09:32, Philippe Mathieu-Daudé wrote:
>> We only support 32-bit TriCore architecture.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   target/tricore/translate.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/tricore/translate.c b/target/tricore/translate.c
>> index 6819b776686..c5b783b6a70 100644
>> --- a/target/tricore/translate.c
>> +++ b/target/tricore/translate.c
>> @@ -5936,7 +5936,7 @@ static void decode_rr_logical_shift(DisasContext 
>> *ctx)
>>           break;
>>       case OPC2_32_RR_CLO:
>>           tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
>> -        tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS);
>> +        tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32);
>>           break;
>>       case OPC2_32_RR_CLO_H:
>>           gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
>> @@ -5948,7 +5948,7 @@ static void decode_rr_logical_shift(DisasContext 
>> *ctx)
>>           gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
>>           break;
>>       case OPC2_32_RR_CLZ:
>> -        tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS);
>> +        tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32);
>>           break;
>>       case OPC2_32_RR_CLZ_H:
>>           gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
> 
> Leave it alone unless you swap /_tl/_i32/ ?

I was expecting something like that, fair enough :)