Here are two small fixes around mhpmevent encoding and reset value.
The first patch is picked from the platform specific event encoding
series[1].

[1] https://lore.kernel.org/qemu-devel/20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com/

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
Changes in v2:
- Replace GENMASK_ULL with MAKE_64BIT_MASK
- Applied RB/AB tags.
- Link to v1: https://lore.kernel.org/r/20250115-pmu_minor_fixes-v1-0-c32388defb02@rivosinc.com

---
Atish Patra (2):
      target/riscv: Fix the hpmevent mask
      target/riscv: Mask out upper sscofpmf bits during validation

 target/riscv/cpu_bits.h | 5 ++---
 target/riscv/pmu.c      | 2 +-
 2 files changed, 3 insertions(+), 4 deletions(-)
---
base-commit: 3f26a7a370c11c7dff68dabcccc19c4e0de901e4
change-id: 20250115-pmu_minor_fixes-7a2b8e3658e4
--
Regards,
Atish patra

On Thu, Feb 6, 2025 at 7:59 PM Atish Patra <atishp@rivosinc.com> wrote:
>
> Here are two small fixes around mhpmevent encoding and reset value.
> The first patch is picked from the platform specific event encoding
> series[1].
>
> [1] https://lore.kernel.org/qemu-devel/20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com/
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
> Changes in v2:
> - Replace GENMASK_ULL with MAKE_64BIT_MASK
> - Applied RB/AB tags.
> - Link to v1: https://lore.kernel.org/r/20250115-pmu_minor_fixes-v1-0-c32388defb02@rivosinc.com
>
> ---
> Atish Patra (2):
>       target/riscv: Fix the hpmevent mask
>       target/riscv: Mask out upper sscofpmf bits during validation
>
>  target/riscv/cpu_bits.h | 5 ++---
>  target/riscv/pmu.c      | 2 +-
>  2 files changed, 3 insertions(+), 4 deletions(-)
> ---
> base-commit: 3f26a7a370c11c7dff68dabcccc19c4e0de901e4
> change-id: 20250115-pmu_minor_fixes-7a2b8e3658e4
> --
> Regards,
> Atish patra
>
>