target/riscv: Fix some RISC-V instruction corner cases

[PATCH 10/12] target/riscv: handle vwadd.wv form vs1 and vs2 overlap

Posted by Anton Blanchard 2 months, 1 week ago

for 2*SEW = 2*SEW op SEW instructions vs2 and vs1 cannot overlap
because it would mean a register is read with two different SEW
settings.

Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 2309d9abd0..312d8b1b81 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -549,7 +549,8 @@ static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int vm)
 {
     return vext_check_ds(s, vd, vs1, vm) &&
            require_vm(vm, vs2) &&
-           require_align(vs2, s->lmul + 1);
+           require_align(vs2, s->lmul + 1) &&
+           !is_overlapped(vs2, 1 << MAX(s->lmul+1, 0), vs1, 1 << MAX(s->lmul, 0));
 }
 
 static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm)
-- 
2.34.1

Re: [PATCH 10/12] target/riscv: handle vwadd.wv form vs1 and vs2 overlap

Posted by Max Chou 1 month, 3 weeks ago

Hi Anton,

This patch violates some coding style rules of QEMU.
You can verify the coding style by running the checkpatch.pl script in 
the QEMU repository.
(ref: 
https://www.qemu.org/docs/master/devel/submitting-a-patch.html#use-the-qemu-coding-style)
The patch 12 also has the same issue.

Thanks,
Max


On 2025/1/26 3:20 PM, Anton Blanchard wrote:
> for 2*SEW = 2*SEW op SEW instructions vs2 and vs1 cannot overlap
> because it would mean a register is read with two different SEW
> settings.
>
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
> ---
>   target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 2309d9abd0..312d8b1b81 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -549,7 +549,8 @@ static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int vm)
>   {
>       return vext_check_ds(s, vd, vs1, vm) &&
>              require_vm(vm, vs2) &&
> -           require_align(vs2, s->lmul + 1);
> +           require_align(vs2, s->lmul + 1) &&
> +           !is_overlapped(vs2, 1 << MAX(s->lmul+1, 0), vs1, 1 << MAX(s->lmul, 0));
>   }
>   
>   static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm)