This series fixes some RISC-V instruction corner cases, specifically
illegal overlaps between mask and source registers, illegal overlaps
between source registers and illegal overlaps between source and
destination registers. These were found by looking at miscompares
between QEMU and the Tenstorrent fork of Whisper which models this
behaviour better than Spike and Sail.

Anton Blanchard (12):
  target/riscv: Source vector registers cannot overlap mask register
  target/riscv: handle vrgather mask and source overlap
  target/riscv: handle vadd.vx form mask and source overlap
  target/riscv: handle vadd.vv form mask and source overlap
  target/riscv: handle vslide1down.vx form mask and source overlap
  target/riscv: handle vzext.vf2 form mask and source overlap
  target/riscv: handle vwadd.vx form mask and source overlap
  target/riscv: handle vwadd.vv form mask and source overlap
  target/riscv: handle vwadd.wv form mask and source overlap
  target/riscv: handle vwadd.wv form vs1 and vs2 overlap
  target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS
  target/riscv: handle overlap in widening instructions with overwrite

 target/riscv/insn_trans/trans_rvv.c.inc | 139 ++++++++++++++++++------
 1 file changed, 108 insertions(+), 31 deletions(-)

-- 
2.34.1

Hi Anton,

I hope you’re doing well.

While reviewing this patchset, I noticed a few missing parts related to 
the mismatched input EEWs encoding constraint.
I also found a few other rvv encoding issues and planned to submit an 
upstream patchset to address them.
However, I think it would be better to merge these fixes into this 
patchset to maintain the series’ cohesion and keep up to date.

If you agree with this approach, I can integrate the fixes and submit a 
v2 of the patchset.
Please let me know your thoughts, and we can discuss the details further.

Thanks,
Max

On 2025/1/26 3:20 PM, Anton Blanchard wrote:
> This series fixes some RISC-V instruction corner cases, specifically
> illegal overlaps between mask and source registers, illegal overlaps
> between source registers and illegal overlaps between source and
> destination registers. These were found by looking at miscompares
> between QEMU and the Tenstorrent fork of Whisper which models this
> behaviour better than Spike and Sail.
>
> Anton Blanchard (12):
>    target/riscv: Source vector registers cannot overlap mask register
>    target/riscv: handle vrgather mask and source overlap
>    target/riscv: handle vadd.vx form mask and source overlap
>    target/riscv: handle vadd.vv form mask and source overlap
>    target/riscv: handle vslide1down.vx form mask and source overlap
>    target/riscv: handle vzext.vf2 form mask and source overlap
>    target/riscv: handle vwadd.vx form mask and source overlap
>    target/riscv: handle vwadd.vv form mask and source overlap
>    target/riscv: handle vwadd.wv form mask and source overlap
>    target/riscv: handle vwadd.wv form vs1 and vs2 overlap
>    target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS
>    target/riscv: handle overlap in widening instructions with overwrite
>
>   target/riscv/insn_trans/trans_rvv.c.inc | 139 ++++++++++++++++++------
>   1 file changed, 108 insertions(+), 31 deletions(-)
>

Hi Max,

On Fri, Feb 28, 2025 at 1:47 AM Max Chou <max.chou@sifive.com> wrote:
> While reviewing this patchset, I noticed a few missing parts related to
> the mismatched input EEWs encoding constraint.
> I also found a few other rvv encoding issues and planned to submit an
> upstream patchset to address them.
> However, I think it would be better to merge these fixes into this
> patchset to maintain the series’ cohesion and keep up to date.
>
> If you agree with this approach, I can integrate the fixes and submit a
> v2 of the patchset.
> Please let me know your thoughts, and we can discuss the details further.

Sorry for not getting back to you earlier but that would be great.

Thanks,
Anton