| 1 | The following changes since commit cf86770c7aa31ebd6e56f4eeb25c34107f92c51e: | 1 | The following changes since commit 92ec7805190313c9e628f8fc4eb4f932c15247bd: |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Merge tag 'pull-request-2025-01-21v2' of https://gitlab.com/thuth/qemu into staging (2025-01-22 09:59:02 -0500) | 3 | Merge tag 'pull-riscv-to-apply-20241031-1' of https://github.com/alistair23/qemu into staging (2024-10-31 16:34:25 +0000) |
| 4 | 4 | ||
| 5 | are available in the Git repository at: | 5 | are available in the Git repository at: |
| 6 | 6 | ||
| 7 | https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20250124 | 7 | https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20241102 |
| 8 | 8 | ||
| 9 | for you to fetch changes up to 3215fe8528de45a1794f0314623cc10bd8e8e19f: | 9 | for you to fetch changes up to 47b54e15bbe78722c62dfafc3e04deded820c05e: |
| 10 | 10 | ||
| 11 | target/loongarch: Dump all generic CSR registers (2025-01-24 14:49:24 +0800) | 11 | target/loongarch: Add steal time support on migration (2024-11-02 15:45:45 +0800) |
| 12 | 12 | ||
| 13 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
| 14 | pull-loongarch-20250124 queue | 14 | pull-loongarch-20241102 |
| 15 | 15 | ||
| 16 | V2: Fix no 'asm/unistd_64.h' build error. | ||
| 17 | Add a new patch (hw/loongarch/boot: Use warn_report when no kernel filename). | ||
| 16 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
| 17 | Bibo Mao (7): | 19 | Bibo Mao (7): |
| 18 | target/loongarch: Add dynamic function access with CSR register | 20 | target/loongarch: Add loongson binary translation feature |
| 19 | target/loongarch: Remove static CSR function setting | 21 | target/loongarch: Implement lbt registers save/restore function |
| 20 | target/loongarch: Add generic csr function type | 22 | target/loongarch/kvm: Implement LoongArch PMU extension |
| 21 | target/loongarch: Add common header file for CSR registers | 23 | linux-headers: Add unistd_64.h |
| 22 | target/loongarch: Add common source file for CSR register | 24 | linux-headers: loongarch: Add kvm_para.h |
| 23 | target/loongarch: Set unused flag with CSR registers | 25 | linux-headers: Update to Linux v6.12-rc5 |
| 24 | target/loongarch: Dump all generic CSR registers | 26 | target/loongarch: Add steal time support on migration |
| 25 | 27 | ||
| 26 | target/loongarch/cpu.c | 96 +++++++++--- | 28 | Song Gao (1): |
| 27 | target/loongarch/csr.c | 129 +++++++++++++++++ | 29 | hw/loongarch/boot: Use warn_report when no kernel filename |
| 28 | target/loongarch/csr.h | 29 ++++ | 30 | |
| 29 | target/loongarch/meson.build | 1 + | 31 | hw/loongarch/boot.c | 5 +- |
| 30 | .../tcg/insn_trans/trans_privileged.c.inc | 161 +++++---------------- | 32 | include/standard-headers/drm/drm_fourcc.h | 43 +++ |
| 31 | target/loongarch/tcg/tcg_loongarch.h | 12 ++ | 33 | include/standard-headers/linux/const.h | 17 ++ |
| 32 | target/loongarch/tcg/translate.c | 5 + | 34 | include/standard-headers/linux/ethtool.h | 226 ++++++++++++++ |
| 33 | 7 files changed, 294 insertions(+), 139 deletions(-) | 35 | include/standard-headers/linux/fuse.h | 22 +- |
| 34 | create mode 100644 target/loongarch/csr.c | 36 | include/standard-headers/linux/input-event-codes.h | 2 + |
| 35 | create mode 100644 target/loongarch/csr.h | 37 | include/standard-headers/linux/pci_regs.h | 41 ++- |
| 36 | create mode 100644 target/loongarch/tcg/tcg_loongarch.h | 38 | include/standard-headers/linux/virtio_balloon.h | 16 +- |
| 39 | include/standard-headers/linux/virtio_gpu.h | 1 + | ||
| 40 | linux-headers/asm-arm64/mman.h | 9 + | ||
| 41 | linux-headers/asm-arm64/unistd.h | 25 +- | ||
| 42 | linux-headers/asm-arm64/unistd_64.h | 324 ++++++++++++++++++++ | ||
| 43 | linux-headers/asm-generic/unistd.h | 6 +- | ||
| 44 | linux-headers/asm-loongarch/kvm.h | 24 ++ | ||
| 45 | linux-headers/asm-loongarch/kvm_para.h | 21 ++ | ||
| 46 | linux-headers/asm-loongarch/unistd.h | 4 +- | ||
| 47 | linux-headers/asm-loongarch/unistd_64.h | 320 ++++++++++++++++++++ | ||
| 48 | linux-headers/asm-riscv/kvm.h | 7 + | ||
| 49 | linux-headers/asm-riscv/unistd.h | 41 +-- | ||
| 50 | linux-headers/asm-riscv/unistd_32.h | 315 ++++++++++++++++++++ | ||
| 51 | linux-headers/asm-riscv/unistd_64.h | 325 +++++++++++++++++++++ | ||
| 52 | linux-headers/asm-x86/kvm.h | 2 + | ||
| 53 | linux-headers/asm-x86/unistd_64.h | 1 + | ||
| 54 | linux-headers/asm-x86/unistd_x32.h | 1 + | ||
| 55 | linux-headers/linux/bits.h | 3 + | ||
| 56 | linux-headers/linux/const.h | 17 ++ | ||
| 57 | linux-headers/linux/iommufd.h | 143 +++++++-- | ||
| 58 | linux-headers/linux/kvm.h | 23 +- | ||
| 59 | linux-headers/linux/mman.h | 1 + | ||
| 60 | linux-headers/linux/psp-sev.h | 28 ++ | ||
| 61 | scripts/update-linux-headers.sh | 7 + | ||
| 62 | target/loongarch/cpu.c | 43 +++ | ||
| 63 | target/loongarch/cpu.h | 23 ++ | ||
| 64 | target/loongarch/kvm/kvm.c | 225 +++++++++++++- | ||
| 65 | target/loongarch/loongarch-qmp-cmds.c | 2 +- | ||
| 66 | target/loongarch/machine.c | 30 +- | ||
| 67 | 36 files changed, 2243 insertions(+), 100 deletions(-) | ||
| 68 | create mode 100644 linux-headers/asm-arm64/unistd_64.h | ||
| 69 | create mode 100644 linux-headers/asm-loongarch/kvm_para.h | ||
| 70 | create mode 100644 linux-headers/asm-loongarch/unistd_64.h | ||
| 71 | create mode 100644 linux-headers/asm-riscv/unistd_32.h | ||
| 72 | create mode 100644 linux-headers/asm-riscv/unistd_64.h | diff view generated by jsdifflib |
| 1 | CSR registers is import system control registers, it had better | 1 | From: Bibo Mao <maobibo@loongson.cn> |
|---|---|---|---|
| 2 | dump all CSR registers when VM is running in system mode. | ||
| 3 | 2 | ||
| 4 | Here is dump output example of CSR registers: | 3 | Loongson Binary Translation (LBT) is used to accelerate binary |
| 5 | CSR000: CRMD b4 PRMD 4 EUEN 0 MISC 0 | 4 | translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM |
| 6 | CSR004: ECFG 71c1c ESTAT 0 ERA 9000000002c31300 BADV 12022c0e0 | 5 | eflags (eflags) and x87 fpu stack pointer (ftop). |
| 7 | CSR008: BADI 2b0000 | 6 | |
| 8 | CSR012: EENTRY 90000000046b0000 | 7 | Now LBT feature is added in kvm mode, not supported in TCG mode since |
| 9 | CSR016: TLBIDX ffffffff8e000228 TLBEHI 120228000 TLBELO0 400000016f19001f TLBELO1 400000016f1a401f | 8 | it is not emulated. Feature variable lbt is added with OnOffAuto type, |
| 10 | CSR024: ASID a0004 PGDL 90000001016f0000 PGDH 9000000004680000 PGD 0 | 9 | If lbt feature is not supported with KVM host, it reports error if there |
| 11 | CSR028: PWCL 5e56e PWCH 2e4 STLBPS e RVACFG 0 | 10 | is lbt=on command line. |
| 12 | CSR032: CPUID 0 PRCFG1 72f8 PRCFG2 3ffff000 PRCFG3 8073f2 | 11 | |
| 13 | CSR048: SAVE0 0 SAVE1 af9c SAVE2 12010d6a8 SAVE3 8300000 | 12 | If there is no any command line about lbt parameter, it checks whether |
| 14 | CSR052: SAVE4 0 SAVE5 0 SAVE6 0 SAVE7 0 | 13 | KVM host supports lbt feature and set the corresponding value in cpucfg. |
| 15 | CSR064: TID 0 TCFG 8f0ca15 TVAL 4cefd8b CNTC fffffffffe688aaa | ||
| 16 | CSR068: TICLR 0 | ||
| 17 | CSR096: LLBCTL 1 | ||
| 18 | CSR136: TLBRENTRY 46ba000 TLBRBADV ffff8000130d81e2 TLBRERA 9000000003585cb8 TLBRSAVE ffff8000130d81e0 | ||
| 19 | CSR140: TLBRELO0 1fe00043 TLBRELO1 40 TLBREHI ffff8000130d800e TLBRPRMD 0 | ||
| 20 | CSR384: DMW0 8000000000000001 DMW1 9000000000000011 DMW2 0 DMW3 0 | ||
| 21 | 14 | ||
| 22 | Signed-off-by: Bibo Mao <maobibo@loongson.cn> | 15 | Signed-off-by: Bibo Mao <maobibo@loongson.cn> |
| 16 | Reviewed-by: Song Gao <gaosong@loongson.cn> | ||
| 17 | Message-Id: <20240929070405.235200-2-maobibo@loongson.cn> | ||
| 18 | Signed-off-by: Song Gao <gaosong@loongson.cn> | ||
| 23 | --- | 19 | --- |
| 24 | target/loongarch/cpu.c | 66 ++++++++++++++++++++++++++++++++---------- | 20 | target/loongarch/cpu.c | 24 +++++++++++ |
| 25 | target/loongarch/csr.c | 2 ++ | 21 | target/loongarch/cpu.h | 6 +++ |
| 26 | target/loongarch/csr.h | 1 + | 22 | target/loongarch/kvm/kvm.c | 57 ++++++++++++++++++++++++++- |
| 27 | 3 files changed, 53 insertions(+), 16 deletions(-) | 23 | target/loongarch/loongarch-qmp-cmds.c | 2 +- |
| 24 | 4 files changed, 87 insertions(+), 2 deletions(-) | ||
| 28 | 25 | ||
| 29 | diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c | 26 | diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c |
| 30 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
| 31 | --- a/target/loongarch/cpu.c | 28 | --- a/target/loongarch/cpu.c |
| 32 | +++ b/target/loongarch/cpu.c | 29 | +++ b/target/loongarch/cpu.c |
| 33 | @@ -XXX,XX +XXX,XX @@ static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) | 30 | @@ -XXX,XX +XXX,XX @@ static void loongarch_set_lasx(Object *obj, bool value, Error **errp) |
| 34 | return oc; | 31 | } |
| 35 | } | 32 | } |
| 36 | 33 | ||
| 37 | +static void loongarch_cpu_dump_csr(CPUState *cs, FILE *f) | 34 | +static bool loongarch_get_lbt(Object *obj, Error **errp) |
| 38 | +{ | 35 | +{ |
| 39 | +#ifndef CONFIG_USER_ONLY | 36 | + return LOONGARCH_CPU(obj)->lbt != ON_OFF_AUTO_OFF; |
| 40 | + CPULoongArchState *env = cpu_env(cs); | ||
| 41 | + CSRInfo *csr_info; | ||
| 42 | + int64_t *addr; | ||
| 43 | + int i, j, len, col = 0; | ||
| 44 | + | ||
| 45 | + qemu_fprintf(f, "\n"); | ||
| 46 | + | ||
| 47 | + /* Dump all generic CSR register */ | ||
| 48 | + for (i = 0; i < LOONGARCH_CSR_DBG; i++) { | ||
| 49 | + csr_info = get_csr(i); | ||
| 50 | + if (!csr_info || (csr_info->flags & CSRFL_UNUSED)) { | ||
| 51 | + if (i == (col + 3)) { | ||
| 52 | + qemu_fprintf(f, "\n"); | ||
| 53 | + } | ||
| 54 | + | ||
| 55 | + continue; | ||
| 56 | + } | ||
| 57 | + | ||
| 58 | + if ((i > (col + 3)) || (i == col)) { | ||
| 59 | + col = i & ~3; | ||
| 60 | + qemu_fprintf(f, " CSR%03d:", col); | ||
| 61 | + } | ||
| 62 | + | ||
| 63 | + addr = (void *)env + csr_info->offset; | ||
| 64 | + qemu_fprintf(f, " %s ", csr_info->name); | ||
| 65 | + len = strlen(csr_info->name); | ||
| 66 | + for (; len < 6; len++) { | ||
| 67 | + qemu_fprintf(f, " "); | ||
| 68 | + } | ||
| 69 | + | ||
| 70 | + qemu_fprintf(f, "%" PRIx64, *addr); | ||
| 71 | + j = find_last_bit((void *)addr, BITS_PER_LONG) & (BITS_PER_LONG - 1); | ||
| 72 | + len += j / 4 + 1; | ||
| 73 | + for (; len < 22; len++) { | ||
| 74 | + qemu_fprintf(f, " "); | ||
| 75 | + } | ||
| 76 | + | ||
| 77 | + if (i == (col + 3)) { | ||
| 78 | + qemu_fprintf(f, "\n"); | ||
| 79 | + } | ||
| 80 | + } | ||
| 81 | + qemu_fprintf(f, "\n"); | ||
| 82 | +#endif | ||
| 83 | +} | 37 | +} |
| 84 | + | 38 | + |
| 85 | static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) | 39 | +static void loongarch_set_lbt(Object *obj, bool value, Error **errp) |
| 40 | +{ | ||
| 41 | + LoongArchCPU *cpu = LOONGARCH_CPU(obj); | ||
| 42 | + | ||
| 43 | + cpu->lbt = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; | ||
| 44 | +} | ||
| 45 | + | ||
| 46 | void loongarch_cpu_post_init(Object *obj) | ||
| 86 | { | 47 | { |
| 87 | CPULoongArchState *env = cpu_env(cs); | 48 | + LoongArchCPU *cpu = LOONGARCH_CPU(obj); |
| 88 | @@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) | 49 | + |
| 89 | } | 50 | object_property_add_bool(obj, "lsx", loongarch_get_lsx, |
| 51 | loongarch_set_lsx); | ||
| 52 | object_property_add_bool(obj, "lasx", loongarch_get_lasx, | ||
| 53 | loongarch_set_lasx); | ||
| 54 | + /* lbt is enabled only in kvm mode, not supported in tcg mode */ | ||
| 55 | + if (kvm_enabled()) { | ||
| 56 | + cpu->lbt = ON_OFF_AUTO_AUTO; | ||
| 57 | + object_property_add_bool(obj, "lbt", loongarch_get_lbt, | ||
| 58 | + loongarch_set_lbt); | ||
| 59 | + object_property_set_description(obj, "lbt", | ||
| 60 | + "Set off to disable Binary Tranlation."); | ||
| 61 | + } else { | ||
| 62 | + cpu->lbt = ON_OFF_AUTO_OFF; | ||
| 63 | + } | ||
| 64 | } | ||
| 65 | |||
| 66 | static void loongarch_cpu_init(Object *obj) | ||
| 67 | diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h | ||
| 68 | index XXXXXXX..XXXXXXX 100644 | ||
| 69 | --- a/target/loongarch/cpu.h | ||
| 70 | +++ b/target/loongarch/cpu.h | ||
| 71 | @@ -XXX,XX +XXX,XX @@ FIELD(CPUCFG2, LLFTP_VER, 15, 3) | ||
| 72 | FIELD(CPUCFG2, LBT_X86, 18, 1) | ||
| 73 | FIELD(CPUCFG2, LBT_ARM, 19, 1) | ||
| 74 | FIELD(CPUCFG2, LBT_MIPS, 20, 1) | ||
| 75 | +FIELD(CPUCFG2, LBT_ALL, 18, 3) | ||
| 76 | FIELD(CPUCFG2, LSPW, 21, 1) | ||
| 77 | FIELD(CPUCFG2, LAM, 22, 1) | ||
| 78 | |||
| 79 | @@ -XXX,XX +XXX,XX @@ struct LoongArchTLB { | ||
| 80 | typedef struct LoongArchTLB LoongArchTLB; | ||
| 81 | #endif | ||
| 82 | |||
| 83 | +enum loongarch_features { | ||
| 84 | + LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */ | ||
| 85 | +}; | ||
| 86 | + | ||
| 87 | typedef struct CPUArchState { | ||
| 88 | uint64_t gpr[32]; | ||
| 89 | uint64_t pc; | ||
| 90 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { | ||
| 91 | CPULoongArchState env; | ||
| 92 | QEMUTimer timer; | ||
| 93 | uint32_t phy_id; | ||
| 94 | + OnOffAuto lbt; | ||
| 95 | |||
| 96 | /* 'compatible' string for this CPU for Linux device trees */ | ||
| 97 | const char *dtb_compatible; | ||
| 98 | diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c | ||
| 99 | index XXXXXXX..XXXXXXX 100644 | ||
| 100 | --- a/target/loongarch/kvm/kvm.c | ||
| 101 | +++ b/target/loongarch/kvm/kvm.c | ||
| 102 | @@ -XXX,XX +XXX,XX @@ | ||
| 103 | #include <sys/ioctl.h> | ||
| 104 | #include <linux/kvm.h> | ||
| 105 | |||
| 106 | +#include "qapi/error.h" | ||
| 107 | #include "qemu/timer.h" | ||
| 108 | #include "qemu/error-report.h" | ||
| 109 | #include "qemu/main-loop.h" | ||
| 110 | @@ -XXX,XX +XXX,XX @@ static void kvm_loongarch_vm_stage_change(void *opaque, bool running, | ||
| 90 | } | 111 | } |
| 91 | 112 | } | |
| 92 | - qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD); | 113 | |
| 93 | - qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD); | 114 | +static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature) |
| 94 | - qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN); | 115 | +{ |
| 95 | - qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT); | 116 | + int ret; |
| 96 | - qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA); | 117 | + struct kvm_device_attr attr; |
| 97 | - qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV); | 118 | + |
| 98 | - qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI); | 119 | + switch (feature) { |
| 99 | - qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY); | 120 | + case LOONGARCH_FEATURE_LBT: |
| 100 | - qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 "," | 121 | + /* |
| 101 | - " PRCFG3=%016" PRIx64 "\n", | 122 | + * Return all if all the LBT features are supported such as: |
| 102 | - env->CSR_PRCFG1, env->CSR_PRCFG2, env->CSR_PRCFG3); | 123 | + * KVM_LOONGARCH_VM_FEAT_X86BT |
| 103 | - qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY); | 124 | + * KVM_LOONGARCH_VM_FEAT_ARMBT |
| 104 | - qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV); | 125 | + * KVM_LOONGARCH_VM_FEAT_MIPSBT |
| 105 | - qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA); | 126 | + */ |
| 106 | - qemu_fprintf(f, "TCFG=%016" PRIx64 "\n", env->CSR_TCFG); | 127 | + attr.group = KVM_LOONGARCH_VM_FEAT_CTRL; |
| 107 | - qemu_fprintf(f, "TVAL=%016" PRIx64 "\n", env->CSR_TVAL); | 128 | + attr.attr = KVM_LOONGARCH_VM_FEAT_X86BT; |
| 108 | + /* csr */ | 129 | + ret = kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr); |
| 109 | + loongarch_cpu_dump_csr(cs, f); | 130 | + attr.attr = KVM_LOONGARCH_VM_FEAT_ARMBT; |
| 110 | 131 | + ret |= kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr); | |
| 111 | /* fpr */ | 132 | + attr.attr = KVM_LOONGARCH_VM_FEAT_MIPSBT; |
| 112 | if (flags & CPU_DUMP_FPU) { | 133 | + ret |= kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr); |
| 113 | diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c | 134 | + return (ret == 0); |
| 135 | + default: | ||
| 136 | + return false; | ||
| 137 | + } | ||
| 138 | +} | ||
| 139 | + | ||
| 140 | +static int kvm_cpu_check_lbt(CPUState *cs, Error **errp) | ||
| 141 | +{ | ||
| 142 | + CPULoongArchState *env = cpu_env(cs); | ||
| 143 | + LoongArchCPU *cpu = LOONGARCH_CPU(cs); | ||
| 144 | + bool kvm_supported; | ||
| 145 | + | ||
| 146 | + kvm_supported = kvm_feature_supported(cs, LOONGARCH_FEATURE_LBT); | ||
| 147 | + if (cpu->lbt == ON_OFF_AUTO_ON) { | ||
| 148 | + if (kvm_supported) { | ||
| 149 | + env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LBT_ALL, 7); | ||
| 150 | + } else { | ||
| 151 | + error_setg(errp, "'lbt' feature not supported by KVM on this host"); | ||
| 152 | + return -ENOTSUP; | ||
| 153 | + } | ||
| 154 | + } else if ((cpu->lbt == ON_OFF_AUTO_AUTO) && kvm_supported) { | ||
| 155 | + env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LBT_ALL, 7); | ||
| 156 | + } | ||
| 157 | + | ||
| 158 | + return 0; | ||
| 159 | +} | ||
| 160 | + | ||
| 161 | int kvm_arch_init_vcpu(CPUState *cs) | ||
| 162 | { | ||
| 163 | uint64_t val; | ||
| 164 | + int ret; | ||
| 165 | + Error *local_err = NULL; | ||
| 166 | |||
| 167 | + ret = 0; | ||
| 168 | qemu_add_vm_change_state_handler(kvm_loongarch_vm_stage_change, cs); | ||
| 169 | |||
| 170 | if (!kvm_get_one_reg(cs, KVM_REG_LOONGARCH_DEBUG_INST, &val)) { | ||
| 171 | brk_insn = val; | ||
| 172 | } | ||
| 173 | |||
| 174 | - return 0; | ||
| 175 | + ret = kvm_cpu_check_lbt(cs, &local_err); | ||
| 176 | + if (ret < 0) { | ||
| 177 | + error_report_err(local_err); | ||
| 178 | + } | ||
| 179 | + return ret; | ||
| 180 | } | ||
| 181 | |||
| 182 | int kvm_arch_destroy_vcpu(CPUState *cs) | ||
| 183 | diff --git a/target/loongarch/loongarch-qmp-cmds.c b/target/loongarch/loongarch-qmp-cmds.c | ||
| 114 | index XXXXXXX..XXXXXXX 100644 | 184 | index XXXXXXX..XXXXXXX 100644 |
| 115 | --- a/target/loongarch/csr.c | 185 | --- a/target/loongarch/loongarch-qmp-cmds.c |
| 116 | +++ b/target/loongarch/csr.c | 186 | +++ b/target/loongarch/loongarch-qmp-cmds.c |
| 117 | @@ -XXX,XX +XXX,XX @@ | 187 | @@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) |
| 118 | 188 | } | |
| 119 | #define CSR_OFF_FUNCS(NAME, FL, RD, WR) \ | 189 | |
| 120 | [LOONGARCH_CSR_##NAME] = { \ | 190 | static const char *cpu_model_advertised_features[] = { |
| 121 | + .name = (stringify(NAME)), \ | 191 | - "lsx", "lasx", NULL |
| 122 | .offset = offsetof(CPULoongArchState, CSR_##NAME), \ | 192 | + "lsx", "lasx", "lbt", NULL |
| 123 | .flags = FL, .readfn = RD, .writefn = WR \ | ||
| 124 | } | ||
| 125 | |||
| 126 | #define CSR_OFF_ARRAY(NAME, N) \ | ||
| 127 | [LOONGARCH_CSR_##NAME(N)] = { \ | ||
| 128 | + .name = (stringify(NAME##N)), \ | ||
| 129 | .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \ | ||
| 130 | .flags = 0, .readfn = NULL, .writefn = NULL \ | ||
| 131 | } | ||
| 132 | diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h | ||
| 133 | index XXXXXXX..XXXXXXX 100644 | ||
| 134 | --- a/target/loongarch/csr.h | ||
| 135 | +++ b/target/loongarch/csr.h | ||
| 136 | @@ -XXX,XX +XXX,XX @@ enum { | ||
| 137 | }; | 193 | }; |
| 138 | 194 | ||
| 139 | typedef struct { | 195 | CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type, |
| 140 | + const char *name; | ||
| 141 | int offset; | ||
| 142 | int flags; | ||
| 143 | GenCSRFunc readfn; | ||
| 144 | -- | 196 | -- |
| 145 | 2.43.5 | 197 | 2.34.1 | diff view generated by jsdifflib |
| 1 | With CSR register, dynamic function access is used for CSR register | 1 | From: Bibo Mao <maobibo@loongson.cn> |
|---|---|---|---|
| 2 | access in TCG mode, so that csr info can be used by other modules. | 2 | |
| 3 | Six registers scr0 - scr3, eflags and ftop are added in percpu vmstate. | ||
| 4 | And two functions kvm_loongarch_get_lbt/kvm_loongarch_put_lbt are added | ||
| 5 | to save/restore lbt registers. | ||
| 3 | 6 | ||
| 4 | Signed-off-by: Bibo Mao <maobibo@loongson.cn> | 7 | Signed-off-by: Bibo Mao <maobibo@loongson.cn> |
| 8 | Reviewed-by: Song Gao <gaosong@loongson.cn> | ||
| 9 | Message-Id: <20240929070405.235200-3-maobibo@loongson.cn> | ||
| 10 | Signed-off-by: Song Gao <gaosong@loongson.cn> | ||
| 5 | --- | 11 | --- |
| 6 | .../tcg/insn_trans/trans_privileged.c.inc | 37 +++++++++++++++++-- | 12 | target/loongarch/cpu.h | 12 ++++++++ |
| 7 | target/loongarch/tcg/tcg_loongarch.h | 12 ++++++ | 13 | target/loongarch/kvm/kvm.c | 62 ++++++++++++++++++++++++++++++++++++++ |
| 8 | target/loongarch/tcg/translate.c | 5 +++ | 14 | target/loongarch/machine.c | 24 +++++++++++++++ |
| 9 | 3 files changed, 51 insertions(+), 3 deletions(-) | 15 | 3 files changed, 98 insertions(+) |
| 10 | create mode 100644 target/loongarch/tcg/tcg_loongarch.h | ||
| 11 | 16 | ||
| 12 | diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 17 | diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h |
| 13 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 14 | --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 19 | --- a/target/loongarch/cpu.h |
| 15 | +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 20 | +++ b/target/loongarch/cpu.h |
| 16 | @@ -XXX,XX +XXX,XX @@ enum { | 21 | @@ -XXX,XX +XXX,XX @@ enum loongarch_features { |
| 17 | #define CSR_OFF(NAME) \ | 22 | LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */ |
| 18 | CSR_OFF_FLAGS(NAME, 0) | 23 | }; |
| 19 | 24 | ||
| 20 | -static const CSRInfo csr_info[] = { | 25 | +typedef struct LoongArchBT { |
| 21 | +static CSRInfo csr_info[] = { | 26 | + /* scratch registers */ |
| 22 | CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB), | 27 | + uint64_t scr0; |
| 23 | CSR_OFF(PRMD), | 28 | + uint64_t scr1; |
| 24 | CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB), | 29 | + uint64_t scr2; |
| 25 | @@ -XXX,XX +XXX,XX @@ static bool check_plv(DisasContext *ctx) | 30 | + uint64_t scr3; |
| 26 | return false; | 31 | + /* loongarch eflags */ |
| 32 | + uint32_t eflags; | ||
| 33 | + uint32_t ftop; | ||
| 34 | +} lbt_t; | ||
| 35 | + | ||
| 36 | typedef struct CPUArchState { | ||
| 37 | uint64_t gpr[32]; | ||
| 38 | uint64_t pc; | ||
| 39 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
| 40 | fpr_t fpr[32]; | ||
| 41 | bool cf[8]; | ||
| 42 | uint32_t fcsr0; | ||
| 43 | + lbt_t lbt; | ||
| 44 | |||
| 45 | uint32_t cpucfg[21]; | ||
| 46 | |||
| 47 | diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c | ||
| 48 | index XXXXXXX..XXXXXXX 100644 | ||
| 49 | --- a/target/loongarch/kvm/kvm.c | ||
| 50 | +++ b/target/loongarch/kvm/kvm.c | ||
| 51 | @@ -XXX,XX +XXX,XX @@ static int kvm_loongarch_put_regs_fp(CPUState *cs) | ||
| 52 | return ret; | ||
| 27 | } | 53 | } |
| 28 | 54 | ||
| 29 | -static const CSRInfo *get_csr(unsigned csr_num) | 55 | +static int kvm_loongarch_put_lbt(CPUState *cs) |
| 30 | +static CSRInfo *get_csr(unsigned csr_num) | ||
| 31 | { | ||
| 32 | - const CSRInfo *csr; | ||
| 33 | + CSRInfo *csr; | ||
| 34 | |||
| 35 | if (csr_num >= ARRAY_SIZE(csr_info)) { | ||
| 36 | return NULL; | ||
| 37 | @@ -XXX,XX +XXX,XX @@ static const CSRInfo *get_csr(unsigned csr_num) | ||
| 38 | return csr; | ||
| 39 | } | ||
| 40 | |||
| 41 | +static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn, | ||
| 42 | + GenCSRWrite writefn) | ||
| 43 | +{ | 56 | +{ |
| 44 | + CSRInfo *csr; | 57 | + CPULoongArchState *env = cpu_env(cs); |
| 58 | + uint64_t val; | ||
| 59 | + int ret; | ||
| 45 | + | 60 | + |
| 46 | + csr = get_csr(csr_num); | 61 | + /* check whether vm support LBT firstly */ |
| 47 | + if (!csr) { | 62 | + if (FIELD_EX32(env->cpucfg[2], CPUCFG2, LBT_ALL) != 7) { |
| 48 | + return false; | 63 | + return 0; |
| 49 | + } | 64 | + } |
| 50 | + | 65 | + |
| 51 | + csr->readfn = readfn; | 66 | + /* set six LBT registers including scr0-scr3, eflags, ftop */ |
| 52 | + csr->writefn = writefn; | 67 | + ret = kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR0, &env->lbt.scr0); |
| 53 | + return true; | 68 | + ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR1, &env->lbt.scr1); |
| 69 | + ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR2, &env->lbt.scr2); | ||
| 70 | + ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR3, &env->lbt.scr3); | ||
| 71 | + /* | ||
| 72 | + * Be cautious, KVM_REG_LOONGARCH_LBT_FTOP is defined as 64-bit however | ||
| 73 | + * lbt.ftop is 32-bit; the same with KVM_REG_LOONGARCH_LBT_EFLAGS register | ||
| 74 | + */ | ||
| 75 | + val = env->lbt.eflags; | ||
| 76 | + ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_EFLAGS, &val); | ||
| 77 | + val = env->lbt.ftop; | ||
| 78 | + ret |= kvm_set_one_reg(cs, KVM_REG_LOONGARCH_LBT_FTOP, &val); | ||
| 79 | + | ||
| 80 | + return ret; | ||
| 54 | +} | 81 | +} |
| 55 | + | 82 | + |
| 56 | +#define SET_CSR_FUNC(NAME, read, write) \ | 83 | +static int kvm_loongarch_get_lbt(CPUState *cs) |
| 57 | + set_csr_trans_func(LOONGARCH_CSR_##NAME, read, write) | 84 | +{ |
| 85 | + CPULoongArchState *env = cpu_env(cs); | ||
| 86 | + uint64_t val; | ||
| 87 | + int ret; | ||
| 58 | + | 88 | + |
| 59 | +void loongarch_csr_translate_init(void) | 89 | + /* check whether vm support LBT firstly */ |
| 90 | + if (FIELD_EX32(env->cpucfg[2], CPUCFG2, LBT_ALL) != 7) { | ||
| 91 | + return 0; | ||
| 92 | + } | ||
| 93 | + | ||
| 94 | + /* get six LBT registers including scr0-scr3, eflags, ftop */ | ||
| 95 | + ret = kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR0, &env->lbt.scr0); | ||
| 96 | + ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR1, &env->lbt.scr1); | ||
| 97 | + ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR2, &env->lbt.scr2); | ||
| 98 | + ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_SCR3, &env->lbt.scr3); | ||
| 99 | + ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_EFLAGS, &val); | ||
| 100 | + env->lbt.eflags = (uint32_t)val; | ||
| 101 | + ret |= kvm_get_one_reg(cs, KVM_REG_LOONGARCH_LBT_FTOP, &val); | ||
| 102 | + env->lbt.ftop = (uint32_t)val; | ||
| 103 | + | ||
| 104 | + return ret; | ||
| 105 | +} | ||
| 106 | + | ||
| 107 | void kvm_arch_reset_vcpu(CPUState *cs) | ||
| 108 | { | ||
| 109 | CPULoongArchState *env = cpu_env(cs); | ||
| 110 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs, Error **errp) | ||
| 111 | return ret; | ||
| 112 | } | ||
| 113 | |||
| 114 | + ret = kvm_loongarch_get_lbt(cs); | ||
| 115 | + if (ret) { | ||
| 116 | + return ret; | ||
| 117 | + } | ||
| 118 | + | ||
| 119 | ret = kvm_loongarch_get_mpstate(cs); | ||
| 120 | return ret; | ||
| 121 | } | ||
| 122 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level, Error **errp) | ||
| 123 | return ret; | ||
| 124 | } | ||
| 125 | |||
| 126 | + ret = kvm_loongarch_put_lbt(cs); | ||
| 127 | + if (ret) { | ||
| 128 | + return ret; | ||
| 129 | + } | ||
| 130 | + | ||
| 131 | ret = kvm_loongarch_put_mpstate(cs); | ||
| 132 | return ret; | ||
| 133 | } | ||
| 134 | diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c | ||
| 135 | index XXXXXXX..XXXXXXX 100644 | ||
| 136 | --- a/target/loongarch/machine.c | ||
| 137 | +++ b/target/loongarch/machine.c | ||
| 138 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lasx = { | ||
| 139 | }, | ||
| 140 | }; | ||
| 141 | |||
| 142 | +static bool lbt_needed(void *opaque) | ||
| 60 | +{ | 143 | +{ |
| 61 | + SET_CSR_FUNC(ESTAT, NULL, gen_helper_csrwr_estat); | 144 | + LoongArchCPU *cpu = opaque; |
| 62 | + SET_CSR_FUNC(ASID, NULL, gen_helper_csrwr_asid); | 145 | + |
| 63 | + SET_CSR_FUNC(PGD, gen_helper_csrrd_pgd, NULL); | 146 | + return !!FIELD_EX64(cpu->env.cpucfg[2], CPUCFG2, LBT_ALL); |
| 64 | + SET_CSR_FUNC(PWCL, NULL, gen_helper_csrwr_pwcl); | ||
| 65 | + SET_CSR_FUNC(CPUID, gen_helper_csrrd_cpuid, NULL); | ||
| 66 | + SET_CSR_FUNC(TCFG, NULL, gen_helper_csrwr_tcfg); | ||
| 67 | + SET_CSR_FUNC(TVAL, gen_helper_csrrd_tval, NULL); | ||
| 68 | + SET_CSR_FUNC(TICLR, NULL, gen_helper_csrwr_ticlr); | ||
| 69 | +} | 147 | +} |
| 70 | +#undef SET_CSR_FUNC | ||
| 71 | + | 148 | + |
| 72 | static bool check_csr_flags(DisasContext *ctx, const CSRInfo *csr, bool write) | 149 | +static const VMStateDescription vmstate_lbt = { |
| 150 | + .name = "cpu/lbt", | ||
| 151 | + .version_id = 0, | ||
| 152 | + .minimum_version_id = 0, | ||
| 153 | + .needed = lbt_needed, | ||
| 154 | + .fields = (const VMStateField[]) { | ||
| 155 | + VMSTATE_UINT64(env.lbt.scr0, LoongArchCPU), | ||
| 156 | + VMSTATE_UINT64(env.lbt.scr1, LoongArchCPU), | ||
| 157 | + VMSTATE_UINT64(env.lbt.scr2, LoongArchCPU), | ||
| 158 | + VMSTATE_UINT64(env.lbt.scr3, LoongArchCPU), | ||
| 159 | + VMSTATE_UINT32(env.lbt.eflags, LoongArchCPU), | ||
| 160 | + VMSTATE_UINT32(env.lbt.ftop, LoongArchCPU), | ||
| 161 | + VMSTATE_END_OF_LIST() | ||
| 162 | + }, | ||
| 163 | +}; | ||
| 164 | + | ||
| 165 | #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) | ||
| 166 | static bool tlb_needed(void *opaque) | ||
| 73 | { | 167 | { |
| 74 | if ((csr->flags & CSRFL_READONLY) && write) { | 168 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_loongarch_cpu = { |
| 75 | diff --git a/target/loongarch/tcg/tcg_loongarch.h b/target/loongarch/tcg/tcg_loongarch.h | 169 | #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) |
| 76 | new file mode 100644 | 170 | &vmstate_tlb, |
| 77 | index XXXXXXX..XXXXXXX | 171 | #endif |
| 78 | --- /dev/null | 172 | + &vmstate_lbt, |
| 79 | +++ b/target/loongarch/tcg/tcg_loongarch.h | 173 | NULL |
| 80 | @@ -XXX,XX +XXX,XX @@ | 174 | } |
| 81 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ | 175 | }; |
| 82 | +/* | ||
| 83 | + * QEMU LoongArch TCG interface | ||
| 84 | + * | ||
| 85 | + * Copyright (c) 2025 Loongson Technology Corporation Limited | ||
| 86 | + */ | ||
| 87 | +#ifndef TARGET_LOONGARCH_TCG_LOONGARCH_H | ||
| 88 | +#define TARGET_LOONGARCH_TCG_LOONGARCH_H | ||
| 89 | + | ||
| 90 | +void loongarch_csr_translate_init(void); | ||
| 91 | + | ||
| 92 | +#endif /* TARGET_LOONGARCH_TCG_LOONGARCH_H */ | ||
| 93 | diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c | ||
| 94 | index XXXXXXX..XXXXXXX 100644 | ||
| 95 | --- a/target/loongarch/tcg/translate.c | ||
| 96 | +++ b/target/loongarch/tcg/translate.c | ||
| 97 | @@ -XXX,XX +XXX,XX @@ | ||
| 98 | #include "exec/log.h" | ||
| 99 | #include "qemu/qemu-print.h" | ||
| 100 | #include "fpu/softfloat.h" | ||
| 101 | +#include "tcg_loongarch.h" | ||
| 102 | #include "translate.h" | ||
| 103 | #include "internals.h" | ||
| 104 | #include "vec.h" | ||
| 105 | @@ -XXX,XX +XXX,XX @@ void loongarch_translate_init(void) | ||
| 106 | offsetof(CPULoongArchState, lladdr), "lladdr"); | ||
| 107 | cpu_llval = tcg_global_mem_new(tcg_env, | ||
| 108 | offsetof(CPULoongArchState, llval), "llval"); | ||
| 109 | + | ||
| 110 | +#ifndef CONFIG_USER_ONLY | ||
| 111 | + loongarch_csr_translate_init(); | ||
| 112 | +#endif | ||
| 113 | } | ||
| 114 | -- | 176 | -- |
| 115 | 2.43.5 | 177 | 2.34.1 | diff view generated by jsdifflib |
| 1 | On LA464, some CSR registers are not used such as CSR_SAVE8 - | 1 | From: Bibo Mao <maobibo@loongson.cn> |
|---|---|---|---|
| 2 | CSR_SAVE15, also CSR registers relative with MCE is not used now. | ||
| 3 | 2 | ||
| 4 | Flag CSRFL_UNUSED is added for these registers, so that it will | 3 | Implement PMU extension for LoongArch kvm mode. Use OnOffAuto type |
| 5 | not dumped. In order to keep compatiblity, these CSR registers are | 4 | variable pmu to check the PMU feature. If the PMU Feature is not supported |
| 6 | not removed since it is used in vmstate already. | 5 | with KVM host, it reports error if there is pmu=on command line. |
| 7 | 6 | ||
| 7 | If there is no any command line about pmu parameter, it checks whether | ||
| 8 | KVM host supports the PMU Feature and set the corresponding value in cpucfg. | ||
| 9 | |||
| 10 | This patch is based on lbt patch located at | ||
| 11 | https://lore.kernel.org/qemu-devel/20240904061859.86615-1-maobibo@loongson.cn | ||
| 12 | |||
| 13 | Co-developed-by: Song Gao <gaosong@loongson.cn> | ||
| 8 | Signed-off-by: Bibo Mao <maobibo@loongson.cn> | 14 | Signed-off-by: Bibo Mao <maobibo@loongson.cn> |
| 15 | Reviewed-by: Song Gao <gaosong@loongson.cn> | ||
| 16 | Message-Id: <20240918082315.2345034-1-maobibo@loongson.cn> | ||
| 17 | Signed-off-by: Song Gao <gaosong@loongson.cn> | ||
| 9 | --- | 18 | --- |
| 10 | target/loongarch/cpu.c | 30 +++++++++++++++++++++++++++++- | 19 | target/loongarch/cpu.c | 19 +++++++++++++ |
| 11 | target/loongarch/csr.c | 13 +++++++++++++ | 20 | target/loongarch/cpu.h | 2 ++ |
| 12 | target/loongarch/csr.h | 2 ++ | 21 | target/loongarch/kvm/kvm.c | 41 +++++++++++++++++++++++++++ |
| 13 | 3 files changed, 44 insertions(+), 1 deletion(-) | 22 | target/loongarch/loongarch-qmp-cmds.c | 2 +- |
| 23 | 4 files changed, 63 insertions(+), 1 deletion(-) | ||
| 14 | 24 | ||
| 15 | diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c | 25 | diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c |
| 16 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/target/loongarch/cpu.c | 27 | --- a/target/loongarch/cpu.c |
| 18 | +++ b/target/loongarch/cpu.c | 28 | +++ b/target/loongarch/cpu.c |
| 19 | @@ -XXX,XX +XXX,XX @@ | 29 | @@ -XXX,XX +XXX,XX @@ static void loongarch_set_lbt(Object *obj, bool value, Error **errp) |
| 20 | #include "cpu.h" | 30 | cpu->lbt = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; |
| 21 | #include "internals.h" | ||
| 22 | #include "fpu/softfloat-helpers.h" | ||
| 23 | -#include "cpu-csr.h" | ||
| 24 | +#include "csr.h" | ||
| 25 | #ifndef CONFIG_USER_ONLY | ||
| 26 | #include "system/reset.h" | ||
| 27 | #endif | ||
| 28 | @@ -XXX,XX +XXX,XX @@ static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) | ||
| 29 | return MMU_DA_IDX; | ||
| 30 | } | 31 | } |
| 31 | 32 | ||
| 32 | +static void loongarch_la464_init_csr(Object *obj) | 33 | +static bool loongarch_get_pmu(Object *obj, Error **errp) |
| 33 | +{ | 34 | +{ |
| 34 | +#ifndef CONFIG_USER_ONLY | 35 | + return LOONGARCH_CPU(obj)->pmu != ON_OFF_AUTO_OFF; |
| 35 | + static bool initialized; | ||
| 36 | + LoongArchCPU *cpu = LOONGARCH_CPU(obj); | ||
| 37 | + CPULoongArchState *env = &cpu->env; | ||
| 38 | + int i, num; | ||
| 39 | + | ||
| 40 | + if (!initialized) { | ||
| 41 | + initialized = true; | ||
| 42 | + num = FIELD_EX64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM); | ||
| 43 | + for (i = num; i < 16; i++) { | ||
| 44 | + set_csr_flag(LOONGARCH_CSR_SAVE(i), CSRFL_UNUSED); | ||
| 45 | + } | ||
| 46 | + set_csr_flag(LOONGARCH_CSR_IMPCTL1, CSRFL_UNUSED); | ||
| 47 | + set_csr_flag(LOONGARCH_CSR_IMPCTL2, CSRFL_UNUSED); | ||
| 48 | + set_csr_flag(LOONGARCH_CSR_MERRCTL, CSRFL_UNUSED); | ||
| 49 | + set_csr_flag(LOONGARCH_CSR_MERRINFO1, CSRFL_UNUSED); | ||
| 50 | + set_csr_flag(LOONGARCH_CSR_MERRINFO2, CSRFL_UNUSED); | ||
| 51 | + set_csr_flag(LOONGARCH_CSR_MERRENTRY, CSRFL_UNUSED); | ||
| 52 | + set_csr_flag(LOONGARCH_CSR_MERRERA, CSRFL_UNUSED); | ||
| 53 | + set_csr_flag(LOONGARCH_CSR_MERRSAVE, CSRFL_UNUSED); | ||
| 54 | + set_csr_flag(LOONGARCH_CSR_CTAG, CSRFL_UNUSED); | ||
| 55 | + } | ||
| 56 | +#endif | ||
| 57 | +} | 36 | +} |
| 58 | + | 37 | + |
| 59 | static void loongarch_la464_initfn(Object *obj) | 38 | +static void loongarch_set_pmu(Object *obj, bool value, Error **errp) |
| 39 | +{ | ||
| 40 | + LoongArchCPU *cpu = LOONGARCH_CPU(obj); | ||
| 41 | + | ||
| 42 | + cpu->pmu = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; | ||
| 43 | +} | ||
| 44 | + | ||
| 45 | void loongarch_cpu_post_init(Object *obj) | ||
| 60 | { | 46 | { |
| 61 | LoongArchCPU *cpu = LOONGARCH_CPU(obj); | 47 | LoongArchCPU *cpu = LOONGARCH_CPU(obj); |
| 62 | @@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj) | 48 | @@ -XXX,XX +XXX,XX @@ void loongarch_cpu_post_init(Object *obj) |
| 63 | env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); | 49 | loongarch_set_lbt); |
| 64 | env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); | 50 | object_property_set_description(obj, "lbt", |
| 65 | 51 | "Set off to disable Binary Tranlation."); | |
| 66 | + loongarch_la464_init_csr(obj); | 52 | + |
| 67 | loongarch_cpu_post_init(obj); | 53 | + cpu->pmu = ON_OFF_AUTO_AUTO; |
| 54 | + object_property_add_bool(obj, "pmu", loongarch_get_pmu, | ||
| 55 | + loongarch_set_pmu); | ||
| 56 | + object_property_set_description(obj, "pmu", | ||
| 57 | + "Set off to performance monitor unit."); | ||
| 58 | + | ||
| 59 | } else { | ||
| 60 | cpu->lbt = ON_OFF_AUTO_OFF; | ||
| 61 | } | ||
| 62 | diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h | ||
| 63 | index XXXXXXX..XXXXXXX 100644 | ||
| 64 | --- a/target/loongarch/cpu.h | ||
| 65 | +++ b/target/loongarch/cpu.h | ||
| 66 | @@ -XXX,XX +XXX,XX @@ typedef struct LoongArchTLB LoongArchTLB; | ||
| 67 | |||
| 68 | enum loongarch_features { | ||
| 69 | LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */ | ||
| 70 | + LOONGARCH_FEATURE_PMU, | ||
| 71 | }; | ||
| 72 | |||
| 73 | typedef struct LoongArchBT { | ||
| 74 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { | ||
| 75 | QEMUTimer timer; | ||
| 76 | uint32_t phy_id; | ||
| 77 | OnOffAuto lbt; | ||
| 78 | + OnOffAuto pmu; | ||
| 79 | |||
| 80 | /* 'compatible' string for this CPU for Linux device trees */ | ||
| 81 | const char *dtb_compatible; | ||
| 82 | diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c | ||
| 83 | index XXXXXXX..XXXXXXX 100644 | ||
| 84 | --- a/target/loongarch/kvm/kvm.c | ||
| 85 | +++ b/target/loongarch/kvm/kvm.c | ||
| 86 | @@ -XXX,XX +XXX,XX @@ static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature) | ||
| 87 | attr.attr = KVM_LOONGARCH_VM_FEAT_MIPSBT; | ||
| 88 | ret |= kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr); | ||
| 89 | return (ret == 0); | ||
| 90 | + | ||
| 91 | + case LOONGARCH_FEATURE_PMU: | ||
| 92 | + attr.group = KVM_LOONGARCH_VM_FEAT_CTRL; | ||
| 93 | + attr.attr = KVM_LOONGARCH_VM_FEAT_PMU; | ||
| 94 | + ret = kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr); | ||
| 95 | + return (ret == 0); | ||
| 96 | + | ||
| 97 | default: | ||
| 98 | return false; | ||
| 99 | } | ||
| 100 | + | ||
| 101 | + return false; | ||
| 68 | } | 102 | } |
| 69 | 103 | ||
| 70 | diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c | 104 | static int kvm_cpu_check_lbt(CPUState *cs, Error **errp) |
| 71 | index XXXXXXX..XXXXXXX 100644 | 105 | @@ -XXX,XX +XXX,XX @@ static int kvm_cpu_check_lbt(CPUState *cs, Error **errp) |
| 72 | --- a/target/loongarch/csr.c | 106 | return 0; |
| 73 | +++ b/target/loongarch/csr.c | ||
| 74 | @@ -XXX,XX +XXX,XX @@ CSRInfo *get_csr(unsigned int csr_num) | ||
| 75 | |||
| 76 | return csr; | ||
| 77 | } | 107 | } |
| 108 | |||
| 109 | +static int kvm_cpu_check_pmu(CPUState *cs, Error **errp) | ||
| 110 | +{ | ||
| 111 | + LoongArchCPU *cpu = LOONGARCH_CPU(cs); | ||
| 112 | + CPULoongArchState *env = cpu_env(cs); | ||
| 113 | + bool kvm_supported; | ||
| 78 | + | 114 | + |
| 79 | +bool set_csr_flag(unsigned int csr_num, int flag) | 115 | + kvm_supported = kvm_feature_supported(cs, LOONGARCH_FEATURE_PMU); |
| 80 | +{ | 116 | + if (cpu->pmu == ON_OFF_AUTO_ON) { |
| 81 | + CSRInfo *csr; | 117 | + if (!kvm_supported) { |
| 82 | + | 118 | + error_setg(errp, "'pmu' feature not supported by KVM on the host"); |
| 83 | + csr = get_csr(csr_num); | 119 | + return -ENOTSUP; |
| 84 | + if (!csr) { | 120 | + } |
| 85 | + return false; | 121 | + } else if (cpu->pmu != ON_OFF_AUTO_AUTO) { |
| 122 | + /* disable pmu if ON_OFF_AUTO_OFF is set */ | ||
| 123 | + kvm_supported = false; | ||
| 86 | + } | 124 | + } |
| 87 | + | 125 | + |
| 88 | + csr->flags |= flag; | 126 | + if (kvm_supported) { |
| 89 | + return true; | 127 | + env->cpucfg[6] = FIELD_DP32(env->cpucfg[6], CPUCFG6, PMP, 1); |
| 128 | + env->cpucfg[6] = FIELD_DP32(env->cpucfg[6], CPUCFG6, PMNUM, 3); | ||
| 129 | + env->cpucfg[6] = FIELD_DP32(env->cpucfg[6], CPUCFG6, PMBITS, 63); | ||
| 130 | + env->cpucfg[6] = FIELD_DP32(env->cpucfg[6], CPUCFG6, UPM, 1); | ||
| 131 | + } | ||
| 132 | + return 0; | ||
| 90 | +} | 133 | +} |
| 91 | diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h | 134 | + |
| 135 | int kvm_arch_init_vcpu(CPUState *cs) | ||
| 136 | { | ||
| 137 | uint64_t val; | ||
| 138 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs) | ||
| 139 | if (ret < 0) { | ||
| 140 | error_report_err(local_err); | ||
| 141 | } | ||
| 142 | + | ||
| 143 | + ret = kvm_cpu_check_pmu(cs, &local_err); | ||
| 144 | + if (ret < 0) { | ||
| 145 | + error_report_err(local_err); | ||
| 146 | + } | ||
| 147 | + | ||
| 148 | return ret; | ||
| 149 | } | ||
| 150 | |||
| 151 | diff --git a/target/loongarch/loongarch-qmp-cmds.c b/target/loongarch/loongarch-qmp-cmds.c | ||
| 92 | index XXXXXXX..XXXXXXX 100644 | 152 | index XXXXXXX..XXXXXXX 100644 |
| 93 | --- a/target/loongarch/csr.h | 153 | --- a/target/loongarch/loongarch-qmp-cmds.c |
| 94 | +++ b/target/loongarch/csr.h | 154 | +++ b/target/loongarch/loongarch-qmp-cmds.c |
| 95 | @@ -XXX,XX +XXX,XX @@ enum { | 155 | @@ -XXX,XX +XXX,XX @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) |
| 96 | CSRFL_READONLY = (1 << 0), | 156 | } |
| 97 | CSRFL_EXITTB = (1 << 1), | 157 | |
| 98 | CSRFL_IO = (1 << 2), | 158 | static const char *cpu_model_advertised_features[] = { |
| 99 | + CSRFL_UNUSED = (1 << 3), | 159 | - "lsx", "lasx", "lbt", NULL |
| 160 | + "lsx", "lasx", "lbt", "pmu", NULL | ||
| 100 | }; | 161 | }; |
| 101 | 162 | ||
| 102 | typedef struct { | 163 | CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type, |
| 103 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
| 104 | } CSRInfo; | ||
| 105 | |||
| 106 | CSRInfo *get_csr(unsigned int csr_num); | ||
| 107 | +bool set_csr_flag(unsigned int csr_num, int flag); | ||
| 108 | #endif /* TARGET_LOONGARCH_CSR_H */ | ||
| 109 | -- | 164 | -- |
| 110 | 2.43.5 | 165 | 2.34.1 | diff view generated by jsdifflib |
| 1 | Common header file csr.h is added here, it can be used by both | 1 | From: Bibo Mao <maobibo@loongson.cn> |
|---|---|---|---|
| 2 | TCG mode and kvm mode. | 2 | |
| 3 | since 6.11, unistd.h includes header file unistd_64.h directly on | ||
| 4 | some platforms, here add unistd_64.h on these platforms. Affected | ||
| 5 | platforms are ARM64, LoongArch64 and Riscv. Otherwise there will | ||
| 6 | be compiling error such as: | ||
| 7 | |||
| 8 | linux-headers/asm/unistd.h:3:10: fatal error: asm/unistd_64.h: No such file or directory | ||
| 9 | #include <asm/unistd_64.h> | ||
| 3 | 10 | ||
| 4 | Signed-off-by: Bibo Mao <maobibo@loongson.cn> | 11 | Signed-off-by: Bibo Mao <maobibo@loongson.cn> |
| 12 | Acked-by: Song Gao <gaosong@loongson.cn> | ||
| 13 | Message-Id: <20241028023809.1554405-2-maobibo@loongson.cn> | ||
| 14 | Signed-off-by: Song Gao <gaosong@loongson.cn> | ||
| 5 | --- | 15 | --- |
| 6 | target/loongarch/csr.h | 25 +++++++++++++++++++ | 16 | scripts/update-linux-headers.sh | 6 ++++++ |
| 7 | .../tcg/insn_trans/trans_privileged.c.inc | 16 +----------- | 17 | 1 file changed, 6 insertions(+) |
| 8 | 2 files changed, 26 insertions(+), 15 deletions(-) | ||
| 9 | create mode 100644 target/loongarch/csr.h | ||
| 10 | 18 | ||
| 11 | diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h | 19 | diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh |
| 12 | new file mode 100644 | 20 | index XXXXXXX..XXXXXXX 100755 |
| 13 | index XXXXXXX..XXXXXXX | 21 | --- a/scripts/update-linux-headers.sh |
| 14 | --- /dev/null | 22 | +++ b/scripts/update-linux-headers.sh |
| 15 | +++ b/target/loongarch/csr.h | 23 | @@ -XXX,XX +XXX,XX @@ EOF |
| 16 | @@ -XXX,XX +XXX,XX @@ | 24 | fi |
| 17 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ | 25 | if [ $arch = arm64 ]; then |
| 18 | +/* | 26 | cp "$hdrdir/include/asm/sve_context.h" "$output/linux-headers/asm-arm64/" |
| 19 | + * Copyright (c) 2025 Loongson Technology Corporation Limited | 27 | + cp "$hdrdir/include/asm/unistd_64.h" "$output/linux-headers/asm-arm64/" |
| 20 | + */ | 28 | fi |
| 21 | + | 29 | if [ $arch = x86 ]; then |
| 22 | +#ifndef TARGET_LOONGARCH_CSR_H | 30 | cp "$hdrdir/include/asm/unistd_32.h" "$output/linux-headers/asm-x86/" |
| 23 | +#define TARGET_LOONGARCH_CSR_H | 31 | @@ -XXX,XX +XXX,XX @@ EOF |
| 24 | + | 32 | fi |
| 25 | +#include "cpu-csr.h" | 33 | if [ $arch = riscv ]; then |
| 26 | + | 34 | cp "$hdrdir/include/asm/ptrace.h" "$output/linux-headers/asm-riscv/" |
| 27 | +typedef void (*GenCSRFunc)(void); | 35 | + cp "$hdrdir/include/asm/unistd_32.h" "$output/linux-headers/asm-riscv/" |
| 28 | +enum { | 36 | + cp "$hdrdir/include/asm/unistd_64.h" "$output/linux-headers/asm-riscv/" |
| 29 | + CSRFL_READONLY = (1 << 0), | 37 | + fi |
| 30 | + CSRFL_EXITTB = (1 << 1), | 38 | + if [ $arch = loongarch ]; then |
| 31 | + CSRFL_IO = (1 << 2), | 39 | + cp "$hdrdir/include/asm/unistd_64.h" "$output/linux-headers/asm-loongarch/" |
| 32 | +}; | 40 | fi |
| 33 | + | 41 | done |
| 34 | +typedef struct { | 42 | arch= |
| 35 | + int offset; | ||
| 36 | + int flags; | ||
| 37 | + GenCSRFunc readfn; | ||
| 38 | + GenCSRFunc writefn; | ||
| 39 | +} CSRInfo; | ||
| 40 | + | ||
| 41 | +#endif /* TARGET_LOONGARCH_CSR_H */ | ||
| 42 | diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | ||
| 43 | index XXXXXXX..XXXXXXX 100644 | ||
| 44 | --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | ||
| 45 | +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | ||
| 46 | @@ -XXX,XX +XXX,XX @@ | ||
| 47 | * LoongArch translation routines for the privileged instructions. | ||
| 48 | */ | ||
| 49 | |||
| 50 | -#include "cpu-csr.h" | ||
| 51 | +#include "csr.h" | ||
| 52 | |||
| 53 | #ifdef CONFIG_USER_ONLY | ||
| 54 | |||
| 55 | @@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle) | ||
| 56 | |||
| 57 | typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env); | ||
| 58 | typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src); | ||
| 59 | -typedef void (*GenCSRFunc)(void); | ||
| 60 | - | ||
| 61 | -typedef struct { | ||
| 62 | - int offset; | ||
| 63 | - int flags; | ||
| 64 | - GenCSRFunc readfn; | ||
| 65 | - GenCSRFunc writefn; | ||
| 66 | -} CSRInfo; | ||
| 67 | - | ||
| 68 | -enum { | ||
| 69 | - CSRFL_READONLY = (1 << 0), | ||
| 70 | - CSRFL_EXITTB = (1 << 1), | ||
| 71 | - CSRFL_IO = (1 << 2), | ||
| 72 | -}; | ||
| 73 | |||
| 74 | #define CSR_OFF_FUNCS(NAME, FL, RD, WR) \ | ||
| 75 | [LOONGARCH_CSR_##NAME] = { \ | ||
| 76 | -- | 43 | -- |
| 77 | 2.43.5 | 44 | 2.34.1 | diff view generated by jsdifflib |
| 1 | Since CSR function setting is done dynamically in TCG mode, remove | 1 | From: Bibo Mao <maobibo@loongson.cn> |
|---|---|---|---|
| 2 | static CSR function setting here. | 2 | |
| 3 | KVM LBT supports on LoongArch depends on the linux-header file | ||
| 4 | kvm_para.h, add header file kvm_para.h here. | ||
| 3 | 5 | ||
| 4 | Signed-off-by: Bibo Mao <maobibo@loongson.cn> | 6 | Signed-off-by: Bibo Mao <maobibo@loongson.cn> |
| 7 | Acked-by: Song Gao <gaosong@loongson.cn> | ||
| 8 | Message-Id: <20241028023809.1554405-3-maobibo@loongson.cn> | ||
| 9 | Signed-off-by: Song Gao <gaosong@loongson.cn> | ||
| 5 | --- | 10 | --- |
| 6 | .../tcg/insn_trans/trans_privileged.c.inc | 16 ++++++++-------- | 11 | scripts/update-linux-headers.sh | 1 + |
| 7 | 1 file changed, 8 insertions(+), 8 deletions(-) | 12 | 1 file changed, 1 insertion(+) |
| 8 | 13 | ||
| 9 | diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 14 | diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh |
| 10 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100755 |
| 11 | --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 16 | --- a/scripts/update-linux-headers.sh |
| 12 | +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 17 | +++ b/scripts/update-linux-headers.sh |
| 13 | @@ -XXX,XX +XXX,XX @@ static CSRInfo csr_info[] = { | 18 | @@ -XXX,XX +XXX,XX @@ EOF |
| 14 | CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB), | 19 | cp "$hdrdir/include/asm/unistd_64.h" "$output/linux-headers/asm-riscv/" |
| 15 | CSR_OFF_FLAGS(MISC, CSRFL_READONLY), | 20 | fi |
| 16 | CSR_OFF(ECFG), | 21 | if [ $arch = loongarch ]; then |
| 17 | - CSR_OFF_FUNCS(ESTAT, CSRFL_EXITTB, NULL, gen_helper_csrwr_estat), | 22 | + cp "$hdrdir/include/asm/kvm_para.h" "$output/linux-headers/asm-loongarch/" |
| 18 | + CSR_OFF_FLAGS(ESTAT, CSRFL_EXITTB), | 23 | cp "$hdrdir/include/asm/unistd_64.h" "$output/linux-headers/asm-loongarch/" |
| 19 | CSR_OFF(ERA), | 24 | fi |
| 20 | CSR_OFF(BADV), | 25 | done |
| 21 | CSR_OFF_FLAGS(BADI, CSRFL_READONLY), | ||
| 22 | @@ -XXX,XX +XXX,XX @@ static CSRInfo csr_info[] = { | ||
| 23 | CSR_OFF(TLBEHI), | ||
| 24 | CSR_OFF(TLBELO0), | ||
| 25 | CSR_OFF(TLBELO1), | ||
| 26 | - CSR_OFF_FUNCS(ASID, CSRFL_EXITTB, NULL, gen_helper_csrwr_asid), | ||
| 27 | + CSR_OFF_FLAGS(ASID, CSRFL_EXITTB), | ||
| 28 | CSR_OFF(PGDL), | ||
| 29 | CSR_OFF(PGDH), | ||
| 30 | - CSR_OFF_FUNCS(PGD, CSRFL_READONLY, gen_helper_csrrd_pgd, NULL), | ||
| 31 | - CSR_OFF_FUNCS(PWCL, 0, NULL, gen_helper_csrwr_pwcl), | ||
| 32 | + CSR_OFF_FLAGS(PGD, CSRFL_READONLY), | ||
| 33 | + CSR_OFF(PWCL), | ||
| 34 | CSR_OFF(PWCH), | ||
| 35 | CSR_OFF(STLBPS), | ||
| 36 | CSR_OFF(RVACFG), | ||
| 37 | - CSR_OFF_FUNCS(CPUID, CSRFL_READONLY, gen_helper_csrrd_cpuid, NULL), | ||
| 38 | + CSR_OFF_FLAGS(CPUID, CSRFL_READONLY), | ||
| 39 | CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY), | ||
| 40 | CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY), | ||
| 41 | CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY), | ||
| 42 | @@ -XXX,XX +XXX,XX @@ static CSRInfo csr_info[] = { | ||
| 43 | CSR_OFF_ARRAY(SAVE, 14), | ||
| 44 | CSR_OFF_ARRAY(SAVE, 15), | ||
| 45 | CSR_OFF(TID), | ||
| 46 | - CSR_OFF_FUNCS(TCFG, CSRFL_IO, NULL, gen_helper_csrwr_tcfg), | ||
| 47 | - CSR_OFF_FUNCS(TVAL, CSRFL_READONLY | CSRFL_IO, gen_helper_csrrd_tval, NULL), | ||
| 48 | + CSR_OFF_FLAGS(TCFG, CSRFL_IO), | ||
| 49 | + CSR_OFF_FLAGS(TVAL, CSRFL_READONLY | CSRFL_IO), | ||
| 50 | CSR_OFF(CNTC), | ||
| 51 | - CSR_OFF_FUNCS(TICLR, CSRFL_IO, NULL, gen_helper_csrwr_ticlr), | ||
| 52 | + CSR_OFF_FLAGS(TICLR, CSRFL_IO), | ||
| 53 | CSR_OFF(LLBCTL), | ||
| 54 | CSR_OFF(IMPCTL1), | ||
| 55 | CSR_OFF(IMPCTL2), | ||
| 56 | -- | 26 | -- |
| 57 | 2.43.5 | 27 | 2.34.1 | diff view generated by jsdifflib |
| 1 | Parameter type TCGv and TCGv_ptr for function GenCSRRead and GenCSRWrite | 1 | When we run “qemu-system-loongarch64 -qmp stdio -vnc none -S”, |
|---|---|---|---|
| 2 | is not used in non-TCG mode. Generic csr function type is added here | 2 | we get an error message “Need kernel filename” and then we can't use qmp cmd to query some information. |
| 3 | with parameter void type, so that it passes to compile with non-TCG mode. | 3 | So, we just throw a warning and then the cpus starts running from address VIRT_FLASH0_BASE. |
| 4 | 4 | ||
| 5 | Signed-off-by: Bibo Mao <maobibo@loongson.cn> | 5 | Signed-off-by: Song Gao <gaosong@loongson.cn> |
| 6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 7 | Message-Id: <20241030012359.4040817-1-gaosong@loongson.cn> | ||
| 6 | --- | 8 | --- |
| 7 | .../tcg/insn_trans/trans_privileged.c.inc | 27 ++++++++++++------- | 9 | hw/loongarch/boot.c | 5 ++--- |
| 8 | 1 file changed, 17 insertions(+), 10 deletions(-) | 10 | 1 file changed, 2 insertions(+), 3 deletions(-) |
| 9 | 11 | ||
| 10 | diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 12 | diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c |
| 11 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
| 12 | --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 14 | --- a/hw/loongarch/boot.c |
| 13 | +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 15 | +++ b/hw/loongarch/boot.c |
| 14 | @@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle) | 16 | @@ -XXX,XX +XXX,XX @@ static void init_boot_rom(struct loongarch_boot_info *info, void *p) |
| 15 | 17 | static void loongarch_direct_kernel_boot(struct loongarch_boot_info *info) | |
| 16 | typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env); | 18 | { |
| 17 | typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src); | 19 | void *p, *bp; |
| 18 | +typedef void (*GenCSRFunc)(void); | 20 | - int64_t kernel_addr = 0; |
| 19 | 21 | + int64_t kernel_addr = VIRT_FLASH0_BASE; | |
| 20 | typedef struct { | 22 | LoongArchCPU *lacpu; |
| 21 | int offset; | 23 | CPUState *cs; |
| 22 | int flags; | 24 | |
| 23 | - GenCSRRead readfn; | 25 | @@ -XXX,XX +XXX,XX @@ static void loongarch_direct_kernel_boot(struct loongarch_boot_info *info) |
| 24 | - GenCSRWrite writefn; | 26 | kernel_addr = load_kernel_info(info); |
| 25 | + GenCSRFunc readfn; | 27 | } else { |
| 26 | + GenCSRFunc writefn; | 28 | if(!qtest_enabled()) { |
| 27 | } CSRInfo; | 29 | - error_report("Need kernel filename\n"); |
| 28 | 30 | - exit(1); | |
| 29 | enum { | 31 | + warn_report("No kernel provided, booting from flash drive."); |
| 30 | @@ -XXX,XX +XXX,XX @@ static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn, | 32 | } |
| 31 | return false; | ||
| 32 | } | 33 | } |
| 33 | 34 | ||
| 34 | - csr->readfn = readfn; | ||
| 35 | - csr->writefn = writefn; | ||
| 36 | + csr->readfn = (GenCSRFunc)readfn; | ||
| 37 | + csr->writefn = (GenCSRFunc)writefn; | ||
| 38 | return true; | ||
| 39 | } | ||
| 40 | |||
| 41 | @@ -XXX,XX +XXX,XX @@ static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a) | ||
| 42 | { | ||
| 43 | TCGv dest; | ||
| 44 | const CSRInfo *csr; | ||
| 45 | + GenCSRRead readfn; | ||
| 46 | |||
| 47 | if (check_plv(ctx)) { | ||
| 48 | return false; | ||
| 49 | @@ -XXX,XX +XXX,XX @@ static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a) | ||
| 50 | } else { | ||
| 51 | check_csr_flags(ctx, csr, false); | ||
| 52 | dest = gpr_dst(ctx, a->rd, EXT_NONE); | ||
| 53 | - if (csr->readfn) { | ||
| 54 | - csr->readfn(dest, tcg_env); | ||
| 55 | + readfn = (GenCSRRead)csr->readfn; | ||
| 56 | + if (readfn) { | ||
| 57 | + readfn(dest, tcg_env); | ||
| 58 | } else { | ||
| 59 | tcg_gen_ld_tl(dest, tcg_env, csr->offset); | ||
| 60 | } | ||
| 61 | @@ -XXX,XX +XXX,XX @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a) | ||
| 62 | { | ||
| 63 | TCGv dest, src1; | ||
| 64 | const CSRInfo *csr; | ||
| 65 | + GenCSRWrite writefn; | ||
| 66 | |||
| 67 | if (check_plv(ctx)) { | ||
| 68 | return false; | ||
| 69 | @@ -XXX,XX +XXX,XX @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a) | ||
| 70 | return false; | ||
| 71 | } | ||
| 72 | src1 = gpr_src(ctx, a->rd, EXT_NONE); | ||
| 73 | - if (csr->writefn) { | ||
| 74 | + writefn = (GenCSRWrite)csr->writefn; | ||
| 75 | + if (writefn) { | ||
| 76 | dest = gpr_dst(ctx, a->rd, EXT_NONE); | ||
| 77 | - csr->writefn(dest, tcg_env, src1); | ||
| 78 | + writefn(dest, tcg_env, src1); | ||
| 79 | } else { | ||
| 80 | dest = tcg_temp_new(); | ||
| 81 | tcg_gen_ld_tl(dest, tcg_env, csr->offset); | ||
| 82 | @@ -XXX,XX +XXX,XX @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a) | ||
| 83 | { | ||
| 84 | TCGv src1, mask, oldv, newv, temp; | ||
| 85 | const CSRInfo *csr; | ||
| 86 | + GenCSRWrite writefn; | ||
| 87 | |||
| 88 | if (check_plv(ctx)) { | ||
| 89 | return false; | ||
| 90 | @@ -XXX,XX +XXX,XX @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a) | ||
| 91 | tcg_gen_andc_tl(temp, oldv, mask); | ||
| 92 | tcg_gen_or_tl(newv, newv, temp); | ||
| 93 | |||
| 94 | - if (csr->writefn) { | ||
| 95 | - csr->writefn(oldv, tcg_env, newv); | ||
| 96 | + writefn = (GenCSRWrite)csr->writefn; | ||
| 97 | + if (writefn) { | ||
| 98 | + writefn(oldv, tcg_env, newv); | ||
| 99 | } else { | ||
| 100 | tcg_gen_st_tl(newv, tcg_env, csr->offset); | ||
| 101 | } | ||
| 102 | -- | 35 | -- |
| 103 | 2.43.5 | 36 | 2.34.1 |
| 37 | |||
| 38 | diff view generated by jsdifflib |
| 1 | Common source file csr.c is added here, it can be used by both | 1 | From: Bibo Mao <maobibo@loongson.cn> |
|---|---|---|---|
| 2 | TCG mode and kvm mode. The common code is removed from file | 2 | |
| 3 | tcg/insn_trans/trans_privileged.c.inc to csrc.c | 3 | With pv steal time supported, VM machine needs get physical address |
| 4 | of each vcpu and notify new host during migration. Here two | ||
| 5 | functions kvm_get_stealtime/kvm_set_stealtime, and guest steal time | ||
| 6 | physical address is only updated on KVM_PUT_FULL_STATE stage. | ||
| 4 | 7 | ||
| 5 | Signed-off-by: Bibo Mao <maobibo@loongson.cn> | 8 | Signed-off-by: Bibo Mao <maobibo@loongson.cn> |
| 9 | Reviewed-by: Song Gao <gaosong@loongson.cn> | ||
| 10 | Message-Id: <20240930064040.753929-1-maobibo@loongson.cn> | ||
| 11 | Signed-off-by: Song Gao <gaosong@loongson.cn> | ||
| 6 | --- | 12 | --- |
| 7 | target/loongarch/csr.c | 114 ++++++++++++++++++ | 13 | target/loongarch/cpu.h | 3 ++ |
| 8 | target/loongarch/csr.h | 1 + | 14 | target/loongarch/kvm/kvm.c | 65 ++++++++++++++++++++++++++++++++++++++ |
| 9 | target/loongarch/meson.build | 1 + | 15 | target/loongarch/machine.c | 6 ++-- |
| 10 | .../tcg/insn_trans/trans_privileged.c.inc | 107 ---------------- | 16 | 3 files changed, 72 insertions(+), 2 deletions(-) |
| 11 | 4 files changed, 116 insertions(+), 107 deletions(-) | ||
| 12 | create mode 100644 target/loongarch/csr.c | ||
| 13 | 17 | ||
| 14 | diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c | 18 | diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h |
| 15 | new file mode 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
| 16 | index XXXXXXX..XXXXXXX | 20 | --- a/target/loongarch/cpu.h |
| 17 | --- /dev/null | 21 | +++ b/target/loongarch/cpu.h |
| 18 | +++ b/target/loongarch/csr.c | 22 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
| 19 | @@ -XXX,XX +XXX,XX @@ | 23 | uint64_t CSR_DBG; |
| 20 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ | 24 | uint64_t CSR_DERA; |
| 21 | +/* | 25 | uint64_t CSR_DSAVE; |
| 22 | + * Copyright (c) 2025 Loongson Technology Corporation Limited | 26 | + struct { |
| 23 | + */ | 27 | + uint64_t guest_addr; |
| 24 | +#include <stddef.h> | 28 | + } stealtime; |
| 25 | +#include "qemu/osdep.h" | 29 | |
| 26 | +#include "cpu.h" | 30 | #ifdef CONFIG_TCG |
| 27 | +#include "csr.h" | 31 | float_status fp_status; |
| 32 | diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c | ||
| 33 | index XXXXXXX..XXXXXXX 100644 | ||
| 34 | --- a/target/loongarch/kvm/kvm.c | ||
| 35 | +++ b/target/loongarch/kvm/kvm.c | ||
| 36 | @@ -XXX,XX +XXX,XX @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { | ||
| 37 | KVM_CAP_LAST_INFO | ||
| 38 | }; | ||
| 39 | |||
| 40 | +static int kvm_get_stealtime(CPUState *cs) | ||
| 41 | +{ | ||
| 42 | + CPULoongArchState *env = cpu_env(cs); | ||
| 43 | + int err; | ||
| 44 | + struct kvm_device_attr attr = { | ||
| 45 | + .group = KVM_LOONGARCH_VCPU_PVTIME_CTRL, | ||
| 46 | + .attr = KVM_LOONGARCH_VCPU_PVTIME_GPA, | ||
| 47 | + .addr = (uint64_t)&env->stealtime.guest_addr, | ||
| 48 | + }; | ||
| 28 | + | 49 | + |
| 29 | +#define CSR_OFF_FUNCS(NAME, FL, RD, WR) \ | 50 | + err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); |
| 30 | + [LOONGARCH_CSR_##NAME] = { \ | 51 | + if (err) { |
| 31 | + .offset = offsetof(CPULoongArchState, CSR_##NAME), \ | 52 | + return 0; |
| 32 | + .flags = FL, .readfn = RD, .writefn = WR \ | ||
| 33 | + } | 53 | + } |
| 34 | + | 54 | + |
| 35 | +#define CSR_OFF_ARRAY(NAME, N) \ | 55 | + err = kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, attr); |
| 36 | + [LOONGARCH_CSR_##NAME(N)] = { \ | 56 | + if (err) { |
| 37 | + .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \ | 57 | + error_report("PVTIME: KVM_GET_DEVICE_ATTR: %s", strerror(errno)); |
| 38 | + .flags = 0, .readfn = NULL, .writefn = NULL \ | 58 | + return err; |
| 39 | + } | 59 | + } |
| 40 | + | 60 | + |
| 41 | +#define CSR_OFF_FLAGS(NAME, FL) CSR_OFF_FUNCS(NAME, FL, NULL, NULL) | 61 | + return 0; |
| 42 | +#define CSR_OFF(NAME) CSR_OFF_FLAGS(NAME, 0) | 62 | +} |
| 43 | + | 63 | + |
| 44 | +static CSRInfo csr_info[] = { | 64 | +static int kvm_set_stealtime(CPUState *cs) |
| 45 | + CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB), | 65 | +{ |
| 46 | + CSR_OFF(PRMD), | 66 | + CPULoongArchState *env = cpu_env(cs); |
| 47 | + CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB), | 67 | + int err; |
| 48 | + CSR_OFF_FLAGS(MISC, CSRFL_READONLY), | 68 | + struct kvm_device_attr attr = { |
| 49 | + CSR_OFF(ECFG), | 69 | + .group = KVM_LOONGARCH_VCPU_PVTIME_CTRL, |
| 50 | + CSR_OFF_FLAGS(ESTAT, CSRFL_EXITTB), | 70 | + .attr = KVM_LOONGARCH_VCPU_PVTIME_GPA, |
| 51 | + CSR_OFF(ERA), | 71 | + .addr = (uint64_t)&env->stealtime.guest_addr, |
| 52 | + CSR_OFF(BADV), | 72 | + }; |
| 53 | + CSR_OFF_FLAGS(BADI, CSRFL_READONLY), | ||
| 54 | + CSR_OFF(EENTRY), | ||
| 55 | + CSR_OFF(TLBIDX), | ||
| 56 | + CSR_OFF(TLBEHI), | ||
| 57 | + CSR_OFF(TLBELO0), | ||
| 58 | + CSR_OFF(TLBELO1), | ||
| 59 | + CSR_OFF_FLAGS(ASID, CSRFL_EXITTB), | ||
| 60 | + CSR_OFF(PGDL), | ||
| 61 | + CSR_OFF(PGDH), | ||
| 62 | + CSR_OFF_FLAGS(PGD, CSRFL_READONLY), | ||
| 63 | + CSR_OFF(PWCL), | ||
| 64 | + CSR_OFF(PWCH), | ||
| 65 | + CSR_OFF(STLBPS), | ||
| 66 | + CSR_OFF(RVACFG), | ||
| 67 | + CSR_OFF_FLAGS(CPUID, CSRFL_READONLY), | ||
| 68 | + CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY), | ||
| 69 | + CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY), | ||
| 70 | + CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY), | ||
| 71 | + CSR_OFF_ARRAY(SAVE, 0), | ||
| 72 | + CSR_OFF_ARRAY(SAVE, 1), | ||
| 73 | + CSR_OFF_ARRAY(SAVE, 2), | ||
| 74 | + CSR_OFF_ARRAY(SAVE, 3), | ||
| 75 | + CSR_OFF_ARRAY(SAVE, 4), | ||
| 76 | + CSR_OFF_ARRAY(SAVE, 5), | ||
| 77 | + CSR_OFF_ARRAY(SAVE, 6), | ||
| 78 | + CSR_OFF_ARRAY(SAVE, 7), | ||
| 79 | + CSR_OFF_ARRAY(SAVE, 8), | ||
| 80 | + CSR_OFF_ARRAY(SAVE, 9), | ||
| 81 | + CSR_OFF_ARRAY(SAVE, 10), | ||
| 82 | + CSR_OFF_ARRAY(SAVE, 11), | ||
| 83 | + CSR_OFF_ARRAY(SAVE, 12), | ||
| 84 | + CSR_OFF_ARRAY(SAVE, 13), | ||
| 85 | + CSR_OFF_ARRAY(SAVE, 14), | ||
| 86 | + CSR_OFF_ARRAY(SAVE, 15), | ||
| 87 | + CSR_OFF(TID), | ||
| 88 | + CSR_OFF_FLAGS(TCFG, CSRFL_IO), | ||
| 89 | + CSR_OFF_FLAGS(TVAL, CSRFL_READONLY | CSRFL_IO), | ||
| 90 | + CSR_OFF(CNTC), | ||
| 91 | + CSR_OFF_FLAGS(TICLR, CSRFL_IO), | ||
| 92 | + CSR_OFF(LLBCTL), | ||
| 93 | + CSR_OFF(IMPCTL1), | ||
| 94 | + CSR_OFF(IMPCTL2), | ||
| 95 | + CSR_OFF(TLBRENTRY), | ||
| 96 | + CSR_OFF(TLBRBADV), | ||
| 97 | + CSR_OFF(TLBRERA), | ||
| 98 | + CSR_OFF(TLBRSAVE), | ||
| 99 | + CSR_OFF(TLBRELO0), | ||
| 100 | + CSR_OFF(TLBRELO1), | ||
| 101 | + CSR_OFF(TLBREHI), | ||
| 102 | + CSR_OFF(TLBRPRMD), | ||
| 103 | + CSR_OFF(MERRCTL), | ||
| 104 | + CSR_OFF(MERRINFO1), | ||
| 105 | + CSR_OFF(MERRINFO2), | ||
| 106 | + CSR_OFF(MERRENTRY), | ||
| 107 | + CSR_OFF(MERRERA), | ||
| 108 | + CSR_OFF(MERRSAVE), | ||
| 109 | + CSR_OFF(CTAG), | ||
| 110 | + CSR_OFF_ARRAY(DMW, 0), | ||
| 111 | + CSR_OFF_ARRAY(DMW, 1), | ||
| 112 | + CSR_OFF_ARRAY(DMW, 2), | ||
| 113 | + CSR_OFF_ARRAY(DMW, 3), | ||
| 114 | + CSR_OFF(DBG), | ||
| 115 | + CSR_OFF(DERA), | ||
| 116 | + CSR_OFF(DSAVE), | ||
| 117 | +}; | ||
| 118 | + | 73 | + |
| 119 | +CSRInfo *get_csr(unsigned int csr_num) | 74 | + err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); |
| 120 | +{ | 75 | + if (err) { |
| 121 | + CSRInfo *csr; | 76 | + return 0; |
| 122 | + | ||
| 123 | + if (csr_num >= ARRAY_SIZE(csr_info)) { | ||
| 124 | + return NULL; | ||
| 125 | + } | 77 | + } |
| 126 | + | 78 | + |
| 127 | + csr = &csr_info[csr_num]; | 79 | + err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr); |
| 128 | + if (csr->offset == 0) { | 80 | + if (err) { |
| 129 | + return NULL; | 81 | + error_report("PVTIME: KVM_SET_DEVICE_ATTR %s with gpa "TARGET_FMT_lx, |
| 82 | + strerror(errno), env->stealtime.guest_addr); | ||
| 83 | + return err; | ||
| 130 | + } | 84 | + } |
| 131 | + | 85 | + |
| 132 | + return csr; | 86 | + return 0; |
| 133 | +} | 87 | +} |
| 134 | diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h | 88 | + |
| 89 | static int kvm_loongarch_get_regs_core(CPUState *cs) | ||
| 90 | { | ||
| 91 | int ret = 0; | ||
| 92 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs, Error **errp) | ||
| 93 | return ret; | ||
| 94 | } | ||
| 95 | |||
| 96 | + ret = kvm_get_stealtime(cs); | ||
| 97 | + if (ret) { | ||
| 98 | + return ret; | ||
| 99 | + } | ||
| 100 | + | ||
| 101 | ret = kvm_loongarch_get_mpstate(cs); | ||
| 102 | return ret; | ||
| 103 | } | ||
| 104 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level, Error **errp) | ||
| 105 | return ret; | ||
| 106 | } | ||
| 107 | |||
| 108 | + if (level >= KVM_PUT_FULL_STATE) { | ||
| 109 | + /* | ||
| 110 | + * only KVM_PUT_FULL_STATE is required, kvm kernel will clear | ||
| 111 | + * guest_addr for KVM_PUT_RESET_STATE | ||
| 112 | + */ | ||
| 113 | + ret = kvm_set_stealtime(cs); | ||
| 114 | + if (ret) { | ||
| 115 | + return ret; | ||
| 116 | + } | ||
| 117 | + } | ||
| 118 | + | ||
| 119 | ret = kvm_loongarch_put_mpstate(cs); | ||
| 120 | return ret; | ||
| 121 | } | ||
| 122 | diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c | ||
| 135 | index XXXXXXX..XXXXXXX 100644 | 123 | index XXXXXXX..XXXXXXX 100644 |
| 136 | --- a/target/loongarch/csr.h | 124 | --- a/target/loongarch/machine.c |
| 137 | +++ b/target/loongarch/csr.h | 125 | +++ b/target/loongarch/machine.c |
| 138 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 126 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_tlb = { |
| 139 | GenCSRFunc writefn; | 127 | /* LoongArch CPU state */ |
| 140 | } CSRInfo; | 128 | const VMStateDescription vmstate_loongarch_cpu = { |
| 141 | 129 | .name = "cpu", | |
| 142 | +CSRInfo *get_csr(unsigned int csr_num); | 130 | - .version_id = 2, |
| 143 | #endif /* TARGET_LOONGARCH_CSR_H */ | 131 | - .minimum_version_id = 2, |
| 144 | diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build | 132 | + .version_id = 3, |
| 145 | index XXXXXXX..XXXXXXX 100644 | 133 | + .minimum_version_id = 3, |
| 146 | --- a/target/loongarch/meson.build | 134 | .fields = (const VMStateField[]) { |
| 147 | +++ b/target/loongarch/meson.build | 135 | VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32), |
| 148 | @@ -XXX,XX +XXX,XX @@ loongarch_system_ss = ss.source_set() | 136 | VMSTATE_UINTTL(env.pc, LoongArchCPU), |
| 149 | loongarch_system_ss.add(files( | 137 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_loongarch_cpu = { |
| 150 | 'arch_dump.c', | 138 | VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU), |
| 151 | 'cpu_helper.c', | 139 | |
| 152 | + 'csr.c', | 140 | VMSTATE_UINT64(kvm_state_counter, LoongArchCPU), |
| 153 | 'loongarch-qmp-cmds.c', | 141 | + /* PV steal time */ |
| 154 | 'machine.c', | 142 | + VMSTATE_UINT64(env.stealtime.guest_addr, LoongArchCPU), |
| 155 | )) | 143 | |
| 156 | diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 144 | VMSTATE_END_OF_LIST() |
| 157 | index XXXXXXX..XXXXXXX 100644 | 145 | }, |
| 158 | --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | ||
| 159 | +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc | ||
| 160 | @@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle) | ||
| 161 | typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env); | ||
| 162 | typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src); | ||
| 163 | |||
| 164 | -#define CSR_OFF_FUNCS(NAME, FL, RD, WR) \ | ||
| 165 | - [LOONGARCH_CSR_##NAME] = { \ | ||
| 166 | - .offset = offsetof(CPULoongArchState, CSR_##NAME), \ | ||
| 167 | - .flags = FL, .readfn = RD, .writefn = WR \ | ||
| 168 | - } | ||
| 169 | - | ||
| 170 | -#define CSR_OFF_ARRAY(NAME, N) \ | ||
| 171 | - [LOONGARCH_CSR_##NAME(N)] = { \ | ||
| 172 | - .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \ | ||
| 173 | - .flags = 0, .readfn = NULL, .writefn = NULL \ | ||
| 174 | - } | ||
| 175 | - | ||
| 176 | -#define CSR_OFF_FLAGS(NAME, FL) \ | ||
| 177 | - CSR_OFF_FUNCS(NAME, FL, NULL, NULL) | ||
| 178 | - | ||
| 179 | -#define CSR_OFF(NAME) \ | ||
| 180 | - CSR_OFF_FLAGS(NAME, 0) | ||
| 181 | - | ||
| 182 | -static CSRInfo csr_info[] = { | ||
| 183 | - CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB), | ||
| 184 | - CSR_OFF(PRMD), | ||
| 185 | - CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB), | ||
| 186 | - CSR_OFF_FLAGS(MISC, CSRFL_READONLY), | ||
| 187 | - CSR_OFF(ECFG), | ||
| 188 | - CSR_OFF_FLAGS(ESTAT, CSRFL_EXITTB), | ||
| 189 | - CSR_OFF(ERA), | ||
| 190 | - CSR_OFF(BADV), | ||
| 191 | - CSR_OFF_FLAGS(BADI, CSRFL_READONLY), | ||
| 192 | - CSR_OFF(EENTRY), | ||
| 193 | - CSR_OFF(TLBIDX), | ||
| 194 | - CSR_OFF(TLBEHI), | ||
| 195 | - CSR_OFF(TLBELO0), | ||
| 196 | - CSR_OFF(TLBELO1), | ||
| 197 | - CSR_OFF_FLAGS(ASID, CSRFL_EXITTB), | ||
| 198 | - CSR_OFF(PGDL), | ||
| 199 | - CSR_OFF(PGDH), | ||
| 200 | - CSR_OFF_FLAGS(PGD, CSRFL_READONLY), | ||
| 201 | - CSR_OFF(PWCL), | ||
| 202 | - CSR_OFF(PWCH), | ||
| 203 | - CSR_OFF(STLBPS), | ||
| 204 | - CSR_OFF(RVACFG), | ||
| 205 | - CSR_OFF_FLAGS(CPUID, CSRFL_READONLY), | ||
| 206 | - CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY), | ||
| 207 | - CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY), | ||
| 208 | - CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY), | ||
| 209 | - CSR_OFF_ARRAY(SAVE, 0), | ||
| 210 | - CSR_OFF_ARRAY(SAVE, 1), | ||
| 211 | - CSR_OFF_ARRAY(SAVE, 2), | ||
| 212 | - CSR_OFF_ARRAY(SAVE, 3), | ||
| 213 | - CSR_OFF_ARRAY(SAVE, 4), | ||
| 214 | - CSR_OFF_ARRAY(SAVE, 5), | ||
| 215 | - CSR_OFF_ARRAY(SAVE, 6), | ||
| 216 | - CSR_OFF_ARRAY(SAVE, 7), | ||
| 217 | - CSR_OFF_ARRAY(SAVE, 8), | ||
| 218 | - CSR_OFF_ARRAY(SAVE, 9), | ||
| 219 | - CSR_OFF_ARRAY(SAVE, 10), | ||
| 220 | - CSR_OFF_ARRAY(SAVE, 11), | ||
| 221 | - CSR_OFF_ARRAY(SAVE, 12), | ||
| 222 | - CSR_OFF_ARRAY(SAVE, 13), | ||
| 223 | - CSR_OFF_ARRAY(SAVE, 14), | ||
| 224 | - CSR_OFF_ARRAY(SAVE, 15), | ||
| 225 | - CSR_OFF(TID), | ||
| 226 | - CSR_OFF_FLAGS(TCFG, CSRFL_IO), | ||
| 227 | - CSR_OFF_FLAGS(TVAL, CSRFL_READONLY | CSRFL_IO), | ||
| 228 | - CSR_OFF(CNTC), | ||
| 229 | - CSR_OFF_FLAGS(TICLR, CSRFL_IO), | ||
| 230 | - CSR_OFF(LLBCTL), | ||
| 231 | - CSR_OFF(IMPCTL1), | ||
| 232 | - CSR_OFF(IMPCTL2), | ||
| 233 | - CSR_OFF(TLBRENTRY), | ||
| 234 | - CSR_OFF(TLBRBADV), | ||
| 235 | - CSR_OFF(TLBRERA), | ||
| 236 | - CSR_OFF(TLBRSAVE), | ||
| 237 | - CSR_OFF(TLBRELO0), | ||
| 238 | - CSR_OFF(TLBRELO1), | ||
| 239 | - CSR_OFF(TLBREHI), | ||
| 240 | - CSR_OFF(TLBRPRMD), | ||
| 241 | - CSR_OFF(MERRCTL), | ||
| 242 | - CSR_OFF(MERRINFO1), | ||
| 243 | - CSR_OFF(MERRINFO2), | ||
| 244 | - CSR_OFF(MERRENTRY), | ||
| 245 | - CSR_OFF(MERRERA), | ||
| 246 | - CSR_OFF(MERRSAVE), | ||
| 247 | - CSR_OFF(CTAG), | ||
| 248 | - CSR_OFF_ARRAY(DMW, 0), | ||
| 249 | - CSR_OFF_ARRAY(DMW, 1), | ||
| 250 | - CSR_OFF_ARRAY(DMW, 2), | ||
| 251 | - CSR_OFF_ARRAY(DMW, 3), | ||
| 252 | - CSR_OFF(DBG), | ||
| 253 | - CSR_OFF(DERA), | ||
| 254 | - CSR_OFF(DSAVE), | ||
| 255 | -}; | ||
| 256 | - | ||
| 257 | static bool check_plv(DisasContext *ctx) | ||
| 258 | { | ||
| 259 | if (ctx->plv == MMU_PLV_USER) { | ||
| 260 | @@ -XXX,XX +XXX,XX @@ static bool check_plv(DisasContext *ctx) | ||
| 261 | return false; | ||
| 262 | } | ||
| 263 | |||
| 264 | -static CSRInfo *get_csr(unsigned csr_num) | ||
| 265 | -{ | ||
| 266 | - CSRInfo *csr; | ||
| 267 | - | ||
| 268 | - if (csr_num >= ARRAY_SIZE(csr_info)) { | ||
| 269 | - return NULL; | ||
| 270 | - } | ||
| 271 | - csr = &csr_info[csr_num]; | ||
| 272 | - if (csr->offset == 0) { | ||
| 273 | - return NULL; | ||
| 274 | - } | ||
| 275 | - return csr; | ||
| 276 | -} | ||
| 277 | - | ||
| 278 | static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn, | ||
| 279 | GenCSRWrite writefn) | ||
| 280 | { | ||
| 281 | -- | 146 | -- |
| 282 | 2.43.5 | 147 | 2.34.1 | diff view generated by jsdifflib |