[PULL 0/7] loongarch-to-apply queue
[PULL v2 00/17] loongarch-to-apply queue
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The following changes since commit cf86770c7aa31ebd6e56f4eeb25c34107f92c51e:
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The following changes since commit 8f6330a807f2642dc2a3cdf33347aa28a4c00a87:
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Merge tag 'pull-request-2025-01-21v2' of https://gitlab.com/thuth/qemu into staging (2025-01-22 09:59:02 -0500)
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Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging (2024-03-06 16:56:20 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20250124
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https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240307
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8
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for you to fetch changes up to 3215fe8528de45a1794f0314623cc10bd8e8e19f:
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for you to fetch changes up to 4dc2edfd6f8abfc38f0ba110502790aa5051b1b5:
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target/loongarch: Dump all generic CSR registers (2025-01-24 14:49:24 +0800)
11
hw/loongarch: Add cells missing from rtc node (2024-03-07 21:58:00 +0800)
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----------------------------------------------------------------
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----------------------------------------------------------------
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pull-loongarch-20250124 queue
14
pull-loongarch-20240307
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----------------------------------------------------------------
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----------------------------------------------------------------
17
Bibo Mao (7):
17
Song Gao (17):
18
target/loongarch: Add dynamic function access with CSR register
18
hw/loongarch: Move boot fucntions to boot.c
19
target/loongarch: Remove static CSR function setting
19
hw/loongarch: Add load initrd
20
target/loongarch: Add generic csr function type
20
hw/loongarch: Add slave cpu boot_code
21
target/loongarch: Add common header file for CSR registers
21
hw/loongarch: Add init_cmdline
22
target/loongarch: Add common source file for CSR register
22
hw/loongarch: Init efi_system_table
23
target/loongarch: Set unused flag with CSR registers
23
hw/loongarch: Init efi_boot_memmap table
24
target/loongarch: Dump all generic CSR registers
24
hw/loongarch: Init efi_initrd table
25
hw/loongarch: Init efi_fdt table
26
hw/loongarch: Fix fdt memory node wrong 'reg'
27
hw/loongarch: fdt adds cpu interrupt controller node
28
hw/loongarch: fdt adds Extend I/O Interrupt Controller
29
hw/loongarch: fdt adds pch_pic Controller
30
hw/loongarch: fdt adds pch_msi Controller
31
hw/loongarch: fdt adds pcie irq_map node
32
hw/loongarch: fdt remove unused irqchip node
33
hw/loongarch: Add cells missing from uart node
34
hw/loongarch: Add cells missing from rtc node
25
35
26
target/loongarch/cpu.c | 96 +++++++++---
36
hw/loongarch/boot.c | 330 +++++++++++++++++++++++++++++++++
27
target/loongarch/csr.c | 129 +++++++++++++++++
37
hw/loongarch/meson.build | 1 +
28
target/loongarch/csr.h | 29 ++++
38
hw/loongarch/virt.c | 363 +++++++++++++++++++++----------------
29
target/loongarch/meson.build | 1 +
39
include/hw/intc/loongarch_extioi.h | 1 +
30
.../tcg/insn_trans/trans_privileged.c.inc | 161 +++++----------------
40
include/hw/loongarch/boot.h | 109 +++++++++++
31
target/loongarch/tcg/tcg_loongarch.h | 12 ++
41
include/hw/loongarch/virt.h | 14 ++
32
target/loongarch/tcg/translate.c | 5 +
42
include/hw/pci-host/ls7a.h | 2 +
33
7 files changed, 294 insertions(+), 139 deletions(-)
43
target/loongarch/cpu.h | 2 +
34
create mode 100644 target/loongarch/csr.c
44
8 files changed, 662 insertions(+), 160 deletions(-)
35
create mode 100644 target/loongarch/csr.h
45
create mode 100644 hw/loongarch/boot.c
36
create mode 100644 target/loongarch/tcg/tcg_loongarch.h
46
create mode 100644 include/hw/loongarch/boot.h
diff view generated by jsdifflib
[PULL 4/7] target/loongarch: Add common header file for CSR registers
[PULL v2 01/17] hw/loongarch: Move boot fucntions to boot.c
1
Common header file csr.h is added here, it can be used by both
1
Move some boot functions to boot.c and struct
2
TCG mode and kvm mode.
2
loongarch_boot_info into struct LoongArchMachineState.
3
3
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
Signed-off-by: Song Gao <gaosong@loongson.cn>
5
Message-Id: <20240301093839.663947-2-gaosong@loongson.cn>
5
---
6
---
6
target/loongarch/csr.h | 25 +++++++++++++++++++
7
hw/loongarch/boot.c | 125 ++++++++++++++++++++++++++++++++++++
7
.../tcg/insn_trans/trans_privileged.c.inc | 16 +-----------
8
hw/loongarch/meson.build | 1 +
8
2 files changed, 26 insertions(+), 15 deletions(-)
9
hw/loongarch/virt.c | 121 +++-------------------------------
9
create mode 100644 target/loongarch/csr.h
10
include/hw/loongarch/boot.h | 21 ++++++
11
include/hw/loongarch/virt.h | 2 +
12
5 files changed, 157 insertions(+), 113 deletions(-)
13
create mode 100644 hw/loongarch/boot.c
14
create mode 100644 include/hw/loongarch/boot.h
10
15
11
diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
16
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
12
new file mode 100644
17
new file mode 100644
13
index XXXXXXX..XXXXXXX
18
index XXXXXXX..XXXXXXX
14
--- /dev/null
19
--- /dev/null
15
+++ b/target/loongarch/csr.h
20
+++ b/hw/loongarch/boot.c
16
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@
17
+/* SPDX-License-Identifier: GPL-2.0-or-later */
22
+/* SPDX-License-Identifier: GPL-2.0-or-later */
18
+/*
23
+/*
19
+ * Copyright (c) 2025 Loongson Technology Corporation Limited
24
+ * LoongArch boot helper functions.
25
+ *
26
+ * Copyright (c) 2023 Loongson Technology Corporation Limited
20
+ */
27
+ */
21
+
28
+
22
+#ifndef TARGET_LOONGARCH_CSR_H
29
+#include "qemu/osdep.h"
23
+#define TARGET_LOONGARCH_CSR_H
30
+#include "qemu/units.h"
24
+
31
+#include "target/loongarch/cpu.h"
25
+#include "cpu-csr.h"
32
+#include "hw/loongarch/virt.h"
26
+
33
+#include "hw/loader.h"
27
+typedef void (*GenCSRFunc)(void);
34
+#include "elf.h"
28
+enum {
35
+#include "qemu/error-report.h"
29
+ CSRFL_READONLY = (1 << 0),
36
+#include "sysemu/reset.h"
30
+ CSRFL_EXITTB = (1 << 1),
37
+
31
+ CSRFL_IO = (1 << 2),
38
+static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
39
+{
40
+ return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS);
41
+}
42
+
43
+static int64_t load_kernel_info(struct loongarch_boot_info *info)
44
+{
45
+ uint64_t kernel_entry, kernel_low, kernel_high;
46
+ ssize_t kernel_size;
47
+
48
+ kernel_size = load_elf(info->kernel_filename, NULL,
49
+ cpu_loongarch_virt_to_phys, NULL,
50
+ &kernel_entry, &kernel_low,
51
+ &kernel_high, NULL, 0,
52
+ EM_LOONGARCH, 1, 0);
53
+
54
+ if (kernel_size < 0) {
55
+ error_report("could not load kernel '%s': %s",
56
+ info->kernel_filename,
57
+ load_elf_strerror(kernel_size));
58
+ exit(1);
59
+ }
60
+ return kernel_entry;
61
+}
62
+
63
+static void reset_load_elf(void *opaque)
64
+{
65
+ LoongArchCPU *cpu = opaque;
66
+ CPULoongArchState *env = &cpu->env;
67
+
68
+ cpu_reset(CPU(cpu));
69
+ if (env->load_elf) {
70
+ cpu_set_pc(CPU(cpu), env->elf_address);
71
+ }
72
+}
73
+
74
+static void fw_cfg_add_kernel_info(struct loongarch_boot_info *info,
75
+ FWCfgState *fw_cfg)
76
+{
77
+ /*
78
+ * Expose the kernel, the command line, and the initrd in fw_cfg.
79
+ * We don't process them here at all, it's all left to the
80
+ * firmware.
81
+ */
82
+ load_image_to_fw_cfg(fw_cfg,
83
+ FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
84
+ info->kernel_filename,
85
+ false);
86
+
87
+ if (info->initrd_filename) {
88
+ load_image_to_fw_cfg(fw_cfg,
89
+ FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
90
+ info->initrd_filename, false);
91
+ }
92
+
93
+ if (info->kernel_cmdline) {
94
+ fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
95
+ strlen(info->kernel_cmdline) + 1);
96
+ fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
97
+ info->kernel_cmdline);
98
+ }
99
+}
100
+
101
+static void loongarch_firmware_boot(LoongArchMachineState *lams,
102
+ struct loongarch_boot_info *info)
103
+{
104
+ fw_cfg_add_kernel_info(info, lams->fw_cfg);
105
+}
106
+
107
+static void loongarch_direct_kernel_boot(struct loongarch_boot_info *info)
108
+{
109
+ int64_t kernel_addr = 0;
110
+ LoongArchCPU *lacpu;
111
+ CPUState *cs;
112
+
113
+ if (info->kernel_filename) {
114
+ kernel_addr = load_kernel_info(info);
115
+ } else {
116
+ error_report("Need kernel filename\n");
117
+ exit(1);
118
+ }
119
+
120
+ CPU_FOREACH(cs) {
121
+ lacpu = LOONGARCH_CPU(cs);
122
+ lacpu->env.load_elf = true;
123
+ lacpu->env.elf_address = kernel_addr;
124
+ }
125
+}
126
+
127
+void loongarch_load_kernel(MachineState *ms, struct loongarch_boot_info *info)
128
+{
129
+ LoongArchMachineState *lams = LOONGARCH_MACHINE(ms);
130
+ int i;
131
+
132
+ /* register reset function */
133
+ for (i = 0; i < ms->smp.cpus; i++) {
134
+ qemu_register_reset(reset_load_elf, LOONGARCH_CPU(qemu_get_cpu(i)));
135
+ }
136
+
137
+ info->kernel_filename = ms->kernel_filename;
138
+ info->kernel_cmdline = ms->kernel_cmdline;
139
+ info->initrd_filename = ms->initrd_filename;
140
+
141
+ if (lams->bios_loaded) {
142
+ loongarch_firmware_boot(lams, info);
143
+ } else {
144
+ loongarch_direct_kernel_boot(info);
145
+ }
146
+}
147
diff --git a/hw/loongarch/meson.build b/hw/loongarch/meson.build
148
index XXXXXXX..XXXXXXX 100644
149
--- a/hw/loongarch/meson.build
150
+++ b/hw/loongarch/meson.build
151
@@ -XXX,XX +XXX,XX @@
152
loongarch_ss = ss.source_set()
153
loongarch_ss.add(files(
154
'fw_cfg.c',
155
+ 'boot.c',
156
))
157
loongarch_ss.add(when: 'CONFIG_LOONGARCH_VIRT', if_true: [files('virt.c'), fdt])
158
loongarch_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-build.c'))
159
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
160
index XXXXXXX..XXXXXXX 100644
161
--- a/hw/loongarch/virt.c
162
+++ b/hw/loongarch/virt.c
163
@@ -XXX,XX +XXX,XX @@
164
#include "hw/block/flash.h"
165
#include "qemu/error-report.h"
166
167
-
168
-struct loaderparams {
169
- uint64_t ram_size;
170
- const char *kernel_filename;
171
- const char *kernel_cmdline;
172
- const char *initrd_filename;
173
-};
174
-
175
static PFlashCFI01 *virt_flash_create1(LoongArchMachineState *lams,
176
const char *name,
177
const char *alias_prop_name)
178
@@ -XXX,XX +XXX,XX @@ static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type)
179
memmap_entries++;
180
}
181
182
-static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
183
-{
184
- return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS);
185
-}
186
-
187
-static int64_t load_kernel_info(const struct loaderparams *loaderparams)
188
-{
189
- uint64_t kernel_entry, kernel_low, kernel_high;
190
- ssize_t kernel_size;
191
-
192
- kernel_size = load_elf(loaderparams->kernel_filename, NULL,
193
- cpu_loongarch_virt_to_phys, NULL,
194
- &kernel_entry, &kernel_low,
195
- &kernel_high, NULL, 0,
196
- EM_LOONGARCH, 1, 0);
197
-
198
- if (kernel_size < 0) {
199
- error_report("could not load kernel '%s': %s",
200
- loaderparams->kernel_filename,
201
- load_elf_strerror(kernel_size));
202
- exit(1);
203
- }
204
- return kernel_entry;
205
-}
206
-
207
static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams)
208
{
209
DeviceState *dev;
210
@@ -XXX,XX +XXX,XX @@ static void loongarch_firmware_init(LoongArchMachineState *lams)
211
}
212
}
213
214
-static void reset_load_elf(void *opaque)
215
-{
216
- LoongArchCPU *cpu = opaque;
217
- CPULoongArchState *env = &cpu->env;
218
-
219
- cpu_reset(CPU(cpu));
220
- if (env->load_elf) {
221
- cpu_set_pc(CPU(cpu), env->elf_address);
222
- }
223
-}
224
-
225
-static void fw_cfg_add_kernel_info(const struct loaderparams *loaderparams,
226
- FWCfgState *fw_cfg)
227
-{
228
- /*
229
- * Expose the kernel, the command line, and the initrd in fw_cfg.
230
- * We don't process them here at all, it's all left to the
231
- * firmware.
232
- */
233
- load_image_to_fw_cfg(fw_cfg,
234
- FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
235
- loaderparams->kernel_filename,
236
- false);
237
-
238
- if (loaderparams->initrd_filename) {
239
- load_image_to_fw_cfg(fw_cfg,
240
- FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
241
- loaderparams->initrd_filename, false);
242
- }
243
-
244
- if (loaderparams->kernel_cmdline) {
245
- fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
246
- strlen(loaderparams->kernel_cmdline) + 1);
247
- fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
248
- loaderparams->kernel_cmdline);
249
- }
250
-}
251
-
252
-static void loongarch_firmware_boot(LoongArchMachineState *lams,
253
- const struct loaderparams *loaderparams)
254
-{
255
- fw_cfg_add_kernel_info(loaderparams, lams->fw_cfg);
256
-}
257
-
258
-static void loongarch_direct_kernel_boot(LoongArchMachineState *lams,
259
- const struct loaderparams *loaderparams)
260
-{
261
- MachineState *machine = MACHINE(lams);
262
- int64_t kernel_addr = 0;
263
- LoongArchCPU *lacpu;
264
- int i;
265
-
266
- kernel_addr = load_kernel_info(loaderparams);
267
- if (!machine->firmware) {
268
- for (i = 0; i < machine->smp.cpus; i++) {
269
- lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
270
- lacpu->env.load_elf = true;
271
- lacpu->env.elf_address = kernel_addr;
272
- }
273
- }
274
-}
275
276
static void loongarch_qemu_write(void *opaque, hwaddr addr,
277
uint64_t val, unsigned size)
278
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
279
MachineClass *mc = MACHINE_GET_CLASS(machine);
280
CPUState *cpu;
281
char *ramName = NULL;
282
- struct loaderparams loaderparams = { };
283
284
if (!cpu_model) {
285
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
286
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
287
sizeof(struct memmap_entry) * (memmap_entries));
288
}
289
fdt_add_fw_cfg_node(lams);
290
- loaderparams.ram_size = ram_size;
291
- loaderparams.kernel_filename = machine->kernel_filename;
292
- loaderparams.kernel_cmdline = machine->kernel_cmdline;
293
- loaderparams.initrd_filename = machine->initrd_filename;
294
- /* load the kernel. */
295
- if (loaderparams.kernel_filename) {
296
- if (lams->bios_loaded) {
297
- loongarch_firmware_boot(lams, &loaderparams);
298
- } else {
299
- loongarch_direct_kernel_boot(lams, &loaderparams);
300
- }
301
- }
302
fdt_add_flash_node(lams);
303
- /* register reset function */
304
- for (i = 0; i < machine->smp.cpus; i++) {
305
- lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
306
- qemu_register_reset(reset_load_elf, lacpu);
307
- }
308
+
309
/* Initialize the IO interrupt subsystem */
310
loongarch_irq_init(lams);
311
fdt_add_irqchip_node(lams);
312
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
313
*/
314
fdt_base = 1 * MiB;
315
qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size);
316
- rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base);
317
+ rom_add_blob_fixed_as("fdt", machine->fdt, lams->fdt_size, fdt_base,
318
+ &address_space_memory);
319
+ qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
320
+ rom_ptr_for_as(&address_space_memory, fdt_base, lams->fdt_size));
321
+
322
+ lams->bootinfo.ram_size = ram_size;
323
+ loongarch_load_kernel(machine, &lams->bootinfo);
324
}
325
326
bool loongarch_is_acpi_enabled(LoongArchMachineState *lams)
327
diff --git a/include/hw/loongarch/boot.h b/include/hw/loongarch/boot.h
328
new file mode 100644
329
index XXXXXXX..XXXXXXX
330
--- /dev/null
331
+++ b/include/hw/loongarch/boot.h
332
@@ -XXX,XX +XXX,XX @@
333
+/* SPDX-License-Identifier: GPL-2.0-or-later */
334
+/*
335
+ * Definitions for LoongArch boot.
336
+ *
337
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
338
+ */
339
+
340
+#ifndef HW_LOONGARCH_BOOT_H
341
+#define HW_LOONGARCH_BOOT_H
342
+
343
+struct loongarch_boot_info {
344
+ uint64_t ram_size;
345
+ const char *kernel_filename;
346
+ const char *kernel_cmdline;
347
+ const char *initrd_filename;
348
+ uint64_t a0, a1, a2;
32
+};
349
+};
33
+
350
+
34
+typedef struct {
351
+void loongarch_load_kernel(MachineState *ms, struct loongarch_boot_info *info);
35
+ int offset;
352
+
36
+ int flags;
353
+#endif /* HW_LOONGARCH_BOOT_H */
37
+ GenCSRFunc readfn;
354
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
38
+ GenCSRFunc writefn;
39
+} CSRInfo;
40
+
41
+#endif /* TARGET_LOONGARCH_CSR_H */
42
diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
43
index XXXXXXX..XXXXXXX 100644
355
index XXXXXXX..XXXXXXX 100644
44
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
356
--- a/include/hw/loongarch/virt.h
45
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
357
+++ b/include/hw/loongarch/virt.h
46
@@ -XXX,XX +XXX,XX @@
358
@@ -XXX,XX +XXX,XX @@
47
* LoongArch translation routines for the privileged instructions.
359
#include "qemu/queue.h"
48
*/
360
#include "hw/intc/loongarch_ipi.h"
49
361
#include "hw/block/flash.h"
50
-#include "cpu-csr.h"
362
+#include "hw/loongarch/boot.h"
51
+#include "csr.h"
363
52
364
#define LOONGARCH_MAX_CPUS 256
53
#ifdef CONFIG_USER_ONLY
365
54
366
@@ -XXX,XX +XXX,XX @@ struct LoongArchMachineState {
55
@@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle)
367
MemoryRegion system_iocsr;
56
368
MemoryRegion iocsr_mem;
57
typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
369
AddressSpace as_iocsr;
58
typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
370
+ struct loongarch_boot_info bootinfo;
59
-typedef void (*GenCSRFunc)(void);
371
};
60
-
372
61
-typedef struct {
373
#define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("virt")
62
- int offset;
63
- int flags;
64
- GenCSRFunc readfn;
65
- GenCSRFunc writefn;
66
-} CSRInfo;
67
-
68
-enum {
69
- CSRFL_READONLY = (1 << 0),
70
- CSRFL_EXITTB = (1 << 1),
71
- CSRFL_IO = (1 << 2),
72
-};
73
74
#define CSR_OFF_FUNCS(NAME, FL, RD, WR) \
75
[LOONGARCH_CSR_##NAME] = { \
76
--
374
--
77
2.43.5
375
2.34.1
diff view generated by jsdifflib
[PULL 5/7] target/loongarch: Add common source file for CSR register
[PULL v2 02/17] hw/loongarch: Add load initrd
1
Common source file csr.c is added here, it can be used by both
1
we load initrd ramdisk after kernel_high address
2
TCG mode and kvm mode. The common code is removed from file
3
tcg/insn_trans/trans_privileged.c.inc to csrc.c
4
2
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
3
Signed-off-by: Song Gao <gaosong@loongson.cn>
4
Message-Id: <20240301093839.663947-3-gaosong@loongson.cn>
6
---
5
---
7
target/loongarch/csr.c | 114 ++++++++++++++++++
6
hw/loongarch/boot.c | 29 ++++++++++++++++++++++++++++-
8
target/loongarch/csr.h | 1 +
7
1 file changed, 28 insertions(+), 1 deletion(-)
9
target/loongarch/meson.build | 1 +
10
.../tcg/insn_trans/trans_privileged.c.inc | 107 ----------------
11
4 files changed, 116 insertions(+), 107 deletions(-)
12
create mode 100644 target/loongarch/csr.c
13
8
14
diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
9
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
15
new file mode 100644
10
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX
11
--- a/hw/loongarch/boot.c
17
--- /dev/null
12
+++ b/hw/loongarch/boot.c
18
+++ b/target/loongarch/csr.c
13
@@ -XXX,XX +XXX,XX @@ static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
19
@@ -XXX,XX +XXX,XX @@
14
20
+/* SPDX-License-Identifier: GPL-2.0-or-later */
15
static int64_t load_kernel_info(struct loongarch_boot_info *info)
21
+/*
16
{
22
+ * Copyright (c) 2025 Loongson Technology Corporation Limited
17
- uint64_t kernel_entry, kernel_low, kernel_high;
23
+ */
18
+ uint64_t kernel_entry, kernel_low, kernel_high, initrd_size;
24
+#include <stddef.h>
19
+ ram_addr_t initrd_offset;
25
+#include "qemu/osdep.h"
20
ssize_t kernel_size;
26
+#include "cpu.h"
21
27
+#include "csr.h"
22
kernel_size = load_elf(info->kernel_filename, NULL,
23
@@ -XXX,XX +XXX,XX @@ static int64_t load_kernel_info(struct loongarch_boot_info *info)
24
load_elf_strerror(kernel_size));
25
exit(1);
26
}
28
+
27
+
29
+#define CSR_OFF_FUNCS(NAME, FL, RD, WR) \
28
+ if (info->initrd_filename) {
30
+ [LOONGARCH_CSR_##NAME] = { \
29
+ initrd_size = get_image_size(info->initrd_filename);
31
+ .offset = offsetof(CPULoongArchState, CSR_##NAME), \
30
+ if (initrd_size > 0) {
32
+ .flags = FL, .readfn = RD, .writefn = WR \
31
+ initrd_offset = ROUND_UP(kernel_high + 4 * kernel_size, 64 * KiB);
32
+
33
+ if (initrd_offset + initrd_size > info->ram_size) {
34
+ error_report("memory too small for initial ram disk '%s'",
35
+ info->initrd_filename);
36
+ exit(1);
37
+ }
38
+
39
+ initrd_size = load_image_targphys(info->initrd_filename, initrd_offset,
40
+ info->ram_size - initrd_offset);
41
+ }
42
+
43
+ if (initrd_size == (target_ulong)-1) {
44
+ error_report("could not load initial ram disk '%s'",
45
+ info->initrd_filename);
46
+ exit(1);
47
+ }
48
+ } else {
49
+ error_report("Need initrd!");
50
+ exit(1);
33
+ }
51
+ }
34
+
52
+
35
+#define CSR_OFF_ARRAY(NAME, N) \
53
return kernel_entry;
36
+ [LOONGARCH_CSR_##NAME(N)] = { \
37
+ .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
38
+ .flags = 0, .readfn = NULL, .writefn = NULL \
39
+ }
40
+
41
+#define CSR_OFF_FLAGS(NAME, FL) CSR_OFF_FUNCS(NAME, FL, NULL, NULL)
42
+#define CSR_OFF(NAME) CSR_OFF_FLAGS(NAME, 0)
43
+
44
+static CSRInfo csr_info[] = {
45
+ CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB),
46
+ CSR_OFF(PRMD),
47
+ CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
48
+ CSR_OFF_FLAGS(MISC, CSRFL_READONLY),
49
+ CSR_OFF(ECFG),
50
+ CSR_OFF_FLAGS(ESTAT, CSRFL_EXITTB),
51
+ CSR_OFF(ERA),
52
+ CSR_OFF(BADV),
53
+ CSR_OFF_FLAGS(BADI, CSRFL_READONLY),
54
+ CSR_OFF(EENTRY),
55
+ CSR_OFF(TLBIDX),
56
+ CSR_OFF(TLBEHI),
57
+ CSR_OFF(TLBELO0),
58
+ CSR_OFF(TLBELO1),
59
+ CSR_OFF_FLAGS(ASID, CSRFL_EXITTB),
60
+ CSR_OFF(PGDL),
61
+ CSR_OFF(PGDH),
62
+ CSR_OFF_FLAGS(PGD, CSRFL_READONLY),
63
+ CSR_OFF(PWCL),
64
+ CSR_OFF(PWCH),
65
+ CSR_OFF(STLBPS),
66
+ CSR_OFF(RVACFG),
67
+ CSR_OFF_FLAGS(CPUID, CSRFL_READONLY),
68
+ CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY),
69
+ CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY),
70
+ CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY),
71
+ CSR_OFF_ARRAY(SAVE, 0),
72
+ CSR_OFF_ARRAY(SAVE, 1),
73
+ CSR_OFF_ARRAY(SAVE, 2),
74
+ CSR_OFF_ARRAY(SAVE, 3),
75
+ CSR_OFF_ARRAY(SAVE, 4),
76
+ CSR_OFF_ARRAY(SAVE, 5),
77
+ CSR_OFF_ARRAY(SAVE, 6),
78
+ CSR_OFF_ARRAY(SAVE, 7),
79
+ CSR_OFF_ARRAY(SAVE, 8),
80
+ CSR_OFF_ARRAY(SAVE, 9),
81
+ CSR_OFF_ARRAY(SAVE, 10),
82
+ CSR_OFF_ARRAY(SAVE, 11),
83
+ CSR_OFF_ARRAY(SAVE, 12),
84
+ CSR_OFF_ARRAY(SAVE, 13),
85
+ CSR_OFF_ARRAY(SAVE, 14),
86
+ CSR_OFF_ARRAY(SAVE, 15),
87
+ CSR_OFF(TID),
88
+ CSR_OFF_FLAGS(TCFG, CSRFL_IO),
89
+ CSR_OFF_FLAGS(TVAL, CSRFL_READONLY | CSRFL_IO),
90
+ CSR_OFF(CNTC),
91
+ CSR_OFF_FLAGS(TICLR, CSRFL_IO),
92
+ CSR_OFF(LLBCTL),
93
+ CSR_OFF(IMPCTL1),
94
+ CSR_OFF(IMPCTL2),
95
+ CSR_OFF(TLBRENTRY),
96
+ CSR_OFF(TLBRBADV),
97
+ CSR_OFF(TLBRERA),
98
+ CSR_OFF(TLBRSAVE),
99
+ CSR_OFF(TLBRELO0),
100
+ CSR_OFF(TLBRELO1),
101
+ CSR_OFF(TLBREHI),
102
+ CSR_OFF(TLBRPRMD),
103
+ CSR_OFF(MERRCTL),
104
+ CSR_OFF(MERRINFO1),
105
+ CSR_OFF(MERRINFO2),
106
+ CSR_OFF(MERRENTRY),
107
+ CSR_OFF(MERRERA),
108
+ CSR_OFF(MERRSAVE),
109
+ CSR_OFF(CTAG),
110
+ CSR_OFF_ARRAY(DMW, 0),
111
+ CSR_OFF_ARRAY(DMW, 1),
112
+ CSR_OFF_ARRAY(DMW, 2),
113
+ CSR_OFF_ARRAY(DMW, 3),
114
+ CSR_OFF(DBG),
115
+ CSR_OFF(DERA),
116
+ CSR_OFF(DSAVE),
117
+};
118
+
119
+CSRInfo *get_csr(unsigned int csr_num)
120
+{
121
+ CSRInfo *csr;
122
+
123
+ if (csr_num >= ARRAY_SIZE(csr_info)) {
124
+ return NULL;
125
+ }
126
+
127
+ csr = &csr_info[csr_num];
128
+ if (csr->offset == 0) {
129
+ return NULL;
130
+ }
131
+
132
+ return csr;
133
+}
134
diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
135
index XXXXXXX..XXXXXXX 100644
136
--- a/target/loongarch/csr.h
137
+++ b/target/loongarch/csr.h
138
@@ -XXX,XX +XXX,XX @@ typedef struct {
139
GenCSRFunc writefn;
140
} CSRInfo;
141
142
+CSRInfo *get_csr(unsigned int csr_num);
143
#endif /* TARGET_LOONGARCH_CSR_H */
144
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
145
index XXXXXXX..XXXXXXX 100644
146
--- a/target/loongarch/meson.build
147
+++ b/target/loongarch/meson.build
148
@@ -XXX,XX +XXX,XX @@ loongarch_system_ss = ss.source_set()
149
loongarch_system_ss.add(files(
150
'arch_dump.c',
151
'cpu_helper.c',
152
+ 'csr.c',
153
'loongarch-qmp-cmds.c',
154
'machine.c',
155
))
156
diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
157
index XXXXXXX..XXXXXXX 100644
158
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
159
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
160
@@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle)
161
typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
162
typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
163
164
-#define CSR_OFF_FUNCS(NAME, FL, RD, WR) \
165
- [LOONGARCH_CSR_##NAME] = { \
166
- .offset = offsetof(CPULoongArchState, CSR_##NAME), \
167
- .flags = FL, .readfn = RD, .writefn = WR \
168
- }
169
-
170
-#define CSR_OFF_ARRAY(NAME, N) \
171
- [LOONGARCH_CSR_##NAME(N)] = { \
172
- .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
173
- .flags = 0, .readfn = NULL, .writefn = NULL \
174
- }
175
-
176
-#define CSR_OFF_FLAGS(NAME, FL) \
177
- CSR_OFF_FUNCS(NAME, FL, NULL, NULL)
178
-
179
-#define CSR_OFF(NAME) \
180
- CSR_OFF_FLAGS(NAME, 0)
181
-
182
-static CSRInfo csr_info[] = {
183
- CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB),
184
- CSR_OFF(PRMD),
185
- CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
186
- CSR_OFF_FLAGS(MISC, CSRFL_READONLY),
187
- CSR_OFF(ECFG),
188
- CSR_OFF_FLAGS(ESTAT, CSRFL_EXITTB),
189
- CSR_OFF(ERA),
190
- CSR_OFF(BADV),
191
- CSR_OFF_FLAGS(BADI, CSRFL_READONLY),
192
- CSR_OFF(EENTRY),
193
- CSR_OFF(TLBIDX),
194
- CSR_OFF(TLBEHI),
195
- CSR_OFF(TLBELO0),
196
- CSR_OFF(TLBELO1),
197
- CSR_OFF_FLAGS(ASID, CSRFL_EXITTB),
198
- CSR_OFF(PGDL),
199
- CSR_OFF(PGDH),
200
- CSR_OFF_FLAGS(PGD, CSRFL_READONLY),
201
- CSR_OFF(PWCL),
202
- CSR_OFF(PWCH),
203
- CSR_OFF(STLBPS),
204
- CSR_OFF(RVACFG),
205
- CSR_OFF_FLAGS(CPUID, CSRFL_READONLY),
206
- CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY),
207
- CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY),
208
- CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY),
209
- CSR_OFF_ARRAY(SAVE, 0),
210
- CSR_OFF_ARRAY(SAVE, 1),
211
- CSR_OFF_ARRAY(SAVE, 2),
212
- CSR_OFF_ARRAY(SAVE, 3),
213
- CSR_OFF_ARRAY(SAVE, 4),
214
- CSR_OFF_ARRAY(SAVE, 5),
215
- CSR_OFF_ARRAY(SAVE, 6),
216
- CSR_OFF_ARRAY(SAVE, 7),
217
- CSR_OFF_ARRAY(SAVE, 8),
218
- CSR_OFF_ARRAY(SAVE, 9),
219
- CSR_OFF_ARRAY(SAVE, 10),
220
- CSR_OFF_ARRAY(SAVE, 11),
221
- CSR_OFF_ARRAY(SAVE, 12),
222
- CSR_OFF_ARRAY(SAVE, 13),
223
- CSR_OFF_ARRAY(SAVE, 14),
224
- CSR_OFF_ARRAY(SAVE, 15),
225
- CSR_OFF(TID),
226
- CSR_OFF_FLAGS(TCFG, CSRFL_IO),
227
- CSR_OFF_FLAGS(TVAL, CSRFL_READONLY | CSRFL_IO),
228
- CSR_OFF(CNTC),
229
- CSR_OFF_FLAGS(TICLR, CSRFL_IO),
230
- CSR_OFF(LLBCTL),
231
- CSR_OFF(IMPCTL1),
232
- CSR_OFF(IMPCTL2),
233
- CSR_OFF(TLBRENTRY),
234
- CSR_OFF(TLBRBADV),
235
- CSR_OFF(TLBRERA),
236
- CSR_OFF(TLBRSAVE),
237
- CSR_OFF(TLBRELO0),
238
- CSR_OFF(TLBRELO1),
239
- CSR_OFF(TLBREHI),
240
- CSR_OFF(TLBRPRMD),
241
- CSR_OFF(MERRCTL),
242
- CSR_OFF(MERRINFO1),
243
- CSR_OFF(MERRINFO2),
244
- CSR_OFF(MERRENTRY),
245
- CSR_OFF(MERRERA),
246
- CSR_OFF(MERRSAVE),
247
- CSR_OFF(CTAG),
248
- CSR_OFF_ARRAY(DMW, 0),
249
- CSR_OFF_ARRAY(DMW, 1),
250
- CSR_OFF_ARRAY(DMW, 2),
251
- CSR_OFF_ARRAY(DMW, 3),
252
- CSR_OFF(DBG),
253
- CSR_OFF(DERA),
254
- CSR_OFF(DSAVE),
255
-};
256
-
257
static bool check_plv(DisasContext *ctx)
258
{
259
if (ctx->plv == MMU_PLV_USER) {
260
@@ -XXX,XX +XXX,XX @@ static bool check_plv(DisasContext *ctx)
261
return false;
262
}
54
}
263
55
264
-static CSRInfo *get_csr(unsigned csr_num)
265
-{
266
- CSRInfo *csr;
267
-
268
- if (csr_num >= ARRAY_SIZE(csr_info)) {
269
- return NULL;
270
- }
271
- csr = &csr_info[csr_num];
272
- if (csr->offset == 0) {
273
- return NULL;
274
- }
275
- return csr;
276
-}
277
-
278
static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn,
279
GenCSRWrite writefn)
280
{
281
--
56
--
282
2.43.5
57
2.34.1
diff view generated by jsdifflib
[PULL 6/7] target/loongarch: Set unused flag with CSR registers
[PULL v2 03/17] hw/loongarch: Add slave cpu boot_code
1
On LA464, some CSR registers are not used such as CSR_SAVE8 -
1
Signed-off-by: Song Gao <gaosong@loongson.cn>
2
CSR_SAVE15, also CSR registers relative with MCE is not used now.
2
Message-Id: <20240301093839.663947-4-gaosong@loongson.cn>
3
---
4
hw/loongarch/boot.c | 70 ++++++++++++++++++++++++++++++++++++++++++++-
5
1 file changed, 69 insertions(+), 1 deletion(-)
3
6
4
Flag CSRFL_UNUSED is added for these registers, so that it will
7
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
5
not dumped. In order to keep compatiblity, these CSR registers are
6
not removed since it is used in vmstate already.
7
8
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
9
---
10
target/loongarch/cpu.c | 30 +++++++++++++++++++++++++++++-
11
target/loongarch/csr.c | 13 +++++++++++++
12
target/loongarch/csr.h | 2 ++
13
3 files changed, 44 insertions(+), 1 deletion(-)
14
15
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
16
index XXXXXXX..XXXXXXX 100644
8
index XXXXXXX..XXXXXXX 100644
17
--- a/target/loongarch/cpu.c
9
--- a/hw/loongarch/boot.c
18
+++ b/target/loongarch/cpu.c
10
+++ b/hw/loongarch/boot.c
19
@@ -XXX,XX +XXX,XX @@
11
@@ -XXX,XX +XXX,XX @@
20
#include "cpu.h"
12
#include "qemu/error-report.h"
21
#include "internals.h"
13
#include "sysemu/reset.h"
22
#include "fpu/softfloat-helpers.h"
14
23
-#include "cpu-csr.h"
15
+static const unsigned int slave_boot_code[] = {
24
+#include "csr.h"
16
+ /* Configure reset ebase. */
25
#ifndef CONFIG_USER_ONLY
17
+ 0x0400302c, /* csrwr $r12,0xc */
26
#include "system/reset.h"
18
+
27
#endif
19
+ /* Disable interrupt. */
28
@@ -XXX,XX +XXX,XX @@ static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch)
20
+ 0x0380100c, /* ori $r12,$r0,0x4 */
29
return MMU_DA_IDX;
21
+ 0x04000180, /* csrxchg $r0,$r12,0x0 */
22
+
23
+ /* Clear mailbox. */
24
+ 0x1400002d, /* lu12i.w $r13,1(0x1) */
25
+ 0x038081ad, /* ori $r13,$r13,0x20 */
26
+ 0x06481da0, /* iocsrwr.d $r0,$r13 */
27
+
28
+ /* Enable IPI interrupt. */
29
+ 0x1400002c, /* lu12i.w $r12,1(0x1) */
30
+ 0x0400118c, /* csrxchg $r12,$r12,0x4 */
31
+ 0x02fffc0c, /* addi.d $r12,$r0,-1(0xfff) */
32
+ 0x1400002d, /* lu12i.w $r13,1(0x1) */
33
+ 0x038011ad, /* ori $r13,$r13,0x4 */
34
+ 0x064819ac, /* iocsrwr.w $r12,$r13 */
35
+ 0x1400002d, /* lu12i.w $r13,1(0x1) */
36
+ 0x038081ad, /* ori $r13,$r13,0x20 */
37
+
38
+ /* Wait for wakeup <.L11>: */
39
+ 0x06488000, /* idle 0x0 */
40
+ 0x03400000, /* andi $r0,$r0,0x0 */
41
+ 0x064809ac, /* iocsrrd.w $r12,$r13 */
42
+ 0x43fff59f, /* beqz $r12,-12(0x7ffff4) # 48 <.L11> */
43
+
44
+ /* Read and clear IPI interrupt. */
45
+ 0x1400002d, /* lu12i.w $r13,1(0x1) */
46
+ 0x064809ac, /* iocsrrd.w $r12,$r13 */
47
+ 0x1400002d, /* lu12i.w $r13,1(0x1) */
48
+ 0x038031ad, /* ori $r13,$r13,0xc */
49
+ 0x064819ac, /* iocsrwr.w $r12,$r13 */
50
+
51
+ /* Disable IPI interrupt. */
52
+ 0x1400002c, /* lu12i.w $r12,1(0x1) */
53
+ 0x04001180, /* csrxchg $r0,$r12,0x4 */
54
+
55
+ /* Read mail buf and jump to specified entry */
56
+ 0x1400002d, /* lu12i.w $r13,1(0x1) */
57
+ 0x038081ad, /* ori $r13,$r13,0x20 */
58
+ 0x06480dac, /* iocsrrd.d $r12,$r13 */
59
+ 0x00150181, /* move $r1,$r12 */
60
+ 0x4c000020, /* jirl $r0,$r1,0 */
61
+};
62
+
63
static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
64
{
65
return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS);
66
@@ -XXX,XX +XXX,XX @@ static void loongarch_firmware_boot(LoongArchMachineState *lams,
67
fw_cfg_add_kernel_info(info, lams->fw_cfg);
30
}
68
}
31
69
32
+static void loongarch_la464_init_csr(Object *obj)
70
+static void init_boot_rom(struct loongarch_boot_info *info, void *p)
33
+{
71
+{
34
+#ifndef CONFIG_USER_ONLY
72
+ memcpy(p, &slave_boot_code, sizeof(slave_boot_code));
35
+ static bool initialized;
73
+ p += sizeof(slave_boot_code);
36
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
37
+ CPULoongArchState *env = &cpu->env;
38
+ int i, num;
39
+
40
+ if (!initialized) {
41
+ initialized = true;
42
+ num = FIELD_EX64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM);
43
+ for (i = num; i < 16; i++) {
44
+ set_csr_flag(LOONGARCH_CSR_SAVE(i), CSRFL_UNUSED);
45
+ }
46
+ set_csr_flag(LOONGARCH_CSR_IMPCTL1, CSRFL_UNUSED);
47
+ set_csr_flag(LOONGARCH_CSR_IMPCTL2, CSRFL_UNUSED);
48
+ set_csr_flag(LOONGARCH_CSR_MERRCTL, CSRFL_UNUSED);
49
+ set_csr_flag(LOONGARCH_CSR_MERRINFO1, CSRFL_UNUSED);
50
+ set_csr_flag(LOONGARCH_CSR_MERRINFO2, CSRFL_UNUSED);
51
+ set_csr_flag(LOONGARCH_CSR_MERRENTRY, CSRFL_UNUSED);
52
+ set_csr_flag(LOONGARCH_CSR_MERRERA, CSRFL_UNUSED);
53
+ set_csr_flag(LOONGARCH_CSR_MERRSAVE, CSRFL_UNUSED);
54
+ set_csr_flag(LOONGARCH_CSR_CTAG, CSRFL_UNUSED);
55
+ }
56
+#endif
57
+}
74
+}
58
+
75
+
59
static void loongarch_la464_initfn(Object *obj)
76
static void loongarch_direct_kernel_boot(struct loongarch_boot_info *info)
60
{
77
{
61
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
78
+ void *p, *bp;
62
@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
79
int64_t kernel_addr = 0;
63
env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
80
LoongArchCPU *lacpu;
64
env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);
81
CPUState *cs;
65
82
@@ -XXX,XX +XXX,XX @@ static void loongarch_direct_kernel_boot(struct loongarch_boot_info *info)
66
+ loongarch_la464_init_csr(obj);
83
exit(1);
67
loongarch_cpu_post_init(obj);
84
}
85
86
+ /* Load 'boot_rom' at [0 - 1MiB] */
87
+ p = g_malloc0(1 * MiB);
88
+ bp = p;
89
+ init_boot_rom(info, p);
90
+ rom_add_blob_fixed("boot_rom", bp, 1 * MiB, 0);
91
+
92
CPU_FOREACH(cs) {
93
lacpu = LOONGARCH_CPU(cs);
94
lacpu->env.load_elf = true;
95
- lacpu->env.elf_address = kernel_addr;
96
+ if (cs == first_cpu) {
97
+ lacpu->env.elf_address = kernel_addr;
98
+ } else {
99
+ lacpu->env.elf_address = 0;
100
+ }
101
+ lacpu->env.boot_info = info;
102
}
103
+
104
+ g_free(bp);
68
}
105
}
69
106
70
diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
107
void loongarch_load_kernel(MachineState *ms, struct loongarch_boot_info *info)
71
index XXXXXXX..XXXXXXX 100644
72
--- a/target/loongarch/csr.c
73
+++ b/target/loongarch/csr.c
74
@@ -XXX,XX +XXX,XX @@ CSRInfo *get_csr(unsigned int csr_num)
75
76
return csr;
77
}
78
+
79
+bool set_csr_flag(unsigned int csr_num, int flag)
80
+{
81
+ CSRInfo *csr;
82
+
83
+ csr = get_csr(csr_num);
84
+ if (!csr) {
85
+ return false;
86
+ }
87
+
88
+ csr->flags |= flag;
89
+ return true;
90
+}
91
diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
92
index XXXXXXX..XXXXXXX 100644
93
--- a/target/loongarch/csr.h
94
+++ b/target/loongarch/csr.h
95
@@ -XXX,XX +XXX,XX @@ enum {
96
CSRFL_READONLY = (1 << 0),
97
CSRFL_EXITTB = (1 << 1),
98
CSRFL_IO = (1 << 2),
99
+ CSRFL_UNUSED = (1 << 3),
100
};
101
102
typedef struct {
103
@@ -XXX,XX +XXX,XX @@ typedef struct {
104
} CSRInfo;
105
106
CSRInfo *get_csr(unsigned int csr_num);
107
+bool set_csr_flag(unsigned int csr_num, int flag);
108
#endif /* TARGET_LOONGARCH_CSR_H */
109
--
108
--
110
2.43.5
109
2.34.1
diff view generated by jsdifflib
New patch
[PULL v2 04/17] hw/loongarch: Add init_cmdline
1
Add init_cmline and set boot_info->a0, a1
1
2
3
Signed-off-by: Song Gao <gaosong@loongson.cn>
4
Message-Id: <20240301093839.663947-5-gaosong@loongson.cn>
5
---
6
hw/loongarch/boot.c | 19 +++++++++++++++++++
7
include/hw/loongarch/virt.h | 2 ++
8
target/loongarch/cpu.h | 2 ++
9
3 files changed, 23 insertions(+)
10
11
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/loongarch/boot.c
14
+++ b/hw/loongarch/boot.c
15
@@ -XXX,XX +XXX,XX @@ static const unsigned int slave_boot_code[] = {
16
0x4c000020, /* jirl $r0,$r1,0 */
17
};
18
19
+static void init_cmdline(struct loongarch_boot_info *info, void *p, void *start)
20
+{
21
+ hwaddr cmdline_addr = (hwaddr)p - (hwaddr)start;
22
+
23
+ info->a0 = 1;
24
+ info->a1 = cmdline_addr;
25
+
26
+ memcpy(p, info->kernel_cmdline, COMMAND_LINE_SIZE);
27
+}
28
+
29
static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
30
{
31
return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS);
32
@@ -XXX,XX +XXX,XX @@ static void reset_load_elf(void *opaque)
33
34
cpu_reset(CPU(cpu));
35
if (env->load_elf) {
36
+    if (cpu == LOONGARCH_CPU(first_cpu)) {
37
+ env->gpr[4] = env->boot_info->a0;
38
+ env->gpr[5] = env->boot_info->a1;
39
+ }
40
cpu_set_pc(CPU(cpu), env->elf_address);
41
}
42
}
43
@@ -XXX,XX +XXX,XX @@ static void loongarch_firmware_boot(LoongArchMachineState *lams,
44
45
static void init_boot_rom(struct loongarch_boot_info *info, void *p)
46
{
47
+ void *start = p;
48
+
49
memcpy(p, &slave_boot_code, sizeof(slave_boot_code));
50
p += sizeof(slave_boot_code);
51
+
52
+ init_cmdline(info, p, start);
53
+ p += COMMAND_LINE_SIZE;
54
}
55
56
static void loongarch_direct_kernel_boot(struct loongarch_boot_info *info)
57
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/include/hw/loongarch/virt.h
60
+++ b/include/hw/loongarch/virt.h
61
@@ -XXX,XX +XXX,XX @@
62
#define VIRT_GED_MEM_ADDR (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN)
63
#define VIRT_GED_REG_ADDR (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN)
64
65
+#define COMMAND_LINE_SIZE 512
66
+
67
struct LoongArchMachineState {
68
/*< private >*/
69
MachineState parent_obj;
70
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
71
index XXXXXXX..XXXXXXX 100644
72
--- a/target/loongarch/cpu.h
73
+++ b/target/loongarch/cpu.h
74
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
75
uint32_t mp_state;
76
/* Store ipistate to access from this struct */
77
DeviceState *ipistate;
78
+
79
+ struct loongarch_boot_info *boot_info;
80
#endif
81
} CPULoongArchState;
82
83
--
84
2.34.1
diff view generated by jsdifflib
New patch
[PULL v2 05/17] hw/loongarch: Init efi_system_table
1
Add init_systab and set boot_info->a2
1
2
3
Signed-off-by: Song Gao <gaosong@loongson.cn>
4
Message-Id: <20240301093839.663947-6-gaosong@loongson.cn>
5
---
6
hw/loongarch/boot.c | 22 +++++++++++++++++
7
include/hw/loongarch/boot.h | 48 +++++++++++++++++++++++++++++++++++++
8
2 files changed, 70 insertions(+)
9
10
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/loongarch/boot.c
13
+++ b/hw/loongarch/boot.c
14
@@ -XXX,XX +XXX,XX @@ static const unsigned int slave_boot_code[] = {
15
0x4c000020, /* jirl $r0,$r1,0 */
16
};
17
18
+static void init_systab(struct loongarch_boot_info *info, void *p, void *start)
19
+{
20
+ struct efi_system_table *systab = p;
21
+
22
+ info->a2 = (uint64_t)p - (uint64_t)start;
23
+
24
+ systab->hdr.signature = EFI_SYSTEM_TABLE_SIGNATURE;
25
+ systab->hdr.revision = EFI_SPECIFICATION_VERSION;
26
+ systab->hdr.revision = sizeof(struct efi_system_table),
27
+ systab->fw_revision = FW_VERSION << 16 | FW_PATCHLEVEL << 8;
28
+ systab->runtime = 0;
29
+ systab->boottime = 0;
30
+ systab->nr_tables = 0;
31
+
32
+ p += ROUND_UP(sizeof(struct efi_system_table), 64);
33
+
34
+ systab->tables = p;
35
+}
36
+
37
static void init_cmdline(struct loongarch_boot_info *info, void *p, void *start)
38
{
39
hwaddr cmdline_addr = (hwaddr)p - (hwaddr)start;
40
@@ -XXX,XX +XXX,XX @@ static void reset_load_elf(void *opaque)
41
    if (cpu == LOONGARCH_CPU(first_cpu)) {
42
env->gpr[4] = env->boot_info->a0;
43
env->gpr[5] = env->boot_info->a1;
44
+ env->gpr[6] = env->boot_info->a2;
45
}
46
cpu_set_pc(CPU(cpu), env->elf_address);
47
}
48
@@ -XXX,XX +XXX,XX @@ static void init_boot_rom(struct loongarch_boot_info *info, void *p)
49
50
init_cmdline(info, p, start);
51
p += COMMAND_LINE_SIZE;
52
+
53
+ init_systab(info, p, start);
54
}
55
56
static void loongarch_direct_kernel_boot(struct loongarch_boot_info *info)
57
diff --git a/include/hw/loongarch/boot.h b/include/hw/loongarch/boot.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/include/hw/loongarch/boot.h
60
+++ b/include/hw/loongarch/boot.h
61
@@ -XXX,XX +XXX,XX @@
62
#ifndef HW_LOONGARCH_BOOT_H
63
#define HW_LOONGARCH_BOOT_H
64
65
+/* UEFI 2.10 */
66
+#define EFI_SYSTEM_TABLE_SIGNATURE 0x5453595320494249
67
+#define EFI_2_100_SYSTEM_TABLE_REVISION ((2<<16) | (100))
68
+#define EFI_SPECIFICATION_VERSION EFI_SYSTEM_TABLE_REVISION
69
+#define EFI_SYSTEM_TABLE_REVISION EFI_2_100_SYSTEM_TABLE_REVISION
70
+
71
+#define FW_VERSION 0x1
72
+#define FW_PATCHLEVEL 0x0
73
+
74
+typedef struct {
75
+ uint8_t b[16];
76
+} efi_guid_t __attribute__((aligned(8)));
77
+
78
+struct efi_config_table {
79
+ efi_guid_t guid;
80
+ uint64_t *ptr;
81
+ const char name[16];
82
+};
83
+
84
+typedef struct {
85
+ uint64_t signature;
86
+ uint32_t revision;
87
+ uint32_t headersize;
88
+ uint32_t crc32;
89
+ uint32_t reserved;
90
+} efi_table_hdr_t;
91
+
92
+struct efi_configuration_table {
93
+ efi_guid_t guid;
94
+ void *table;
95
+};
96
+
97
+struct efi_system_table {
98
+ efi_table_hdr_t hdr;
99
+ uint64_t fw_vendor; /* physical addr of CHAR16 vendor string */
100
+ uint32_t fw_revision;
101
+ uint64_t con_in_handle;
102
+ uint64_t *con_in;
103
+ uint64_t con_out_handle;
104
+ uint64_t *con_out;
105
+ uint64_t stderr_handle;
106
+ uint64_t stderr;
107
+ uint64_t *runtime;
108
+ uint64_t *boottime;
109
+ uint64_t nr_tables;
110
+ struct efi_configuration_table *tables;
111
+};
112
+
113
struct loongarch_boot_info {
114
uint64_t ram_size;
115
const char *kernel_filename;
116
--
117
2.34.1
diff view generated by jsdifflib
New patch
[PULL v2 06/17] hw/loongarch: Init efi_boot_memmap table
1
Signed-off-by: Song Gao <gaosong@loongson.cn>
2
Message-Id: <20240301093839.663947-7-gaosong@loongson.cn>
3
---
4
hw/loongarch/boot.c | 39 +++++++++++++++++++++++++++++++++++++
5
hw/loongarch/virt.c | 11 ++---------
6
include/hw/loongarch/boot.h | 27 +++++++++++++++++++++++++
7
include/hw/loongarch/virt.h | 10 ++++++++++
8
4 files changed, 78 insertions(+), 9 deletions(-)
1
9
10
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/loongarch/boot.c
13
+++ b/hw/loongarch/boot.c
14
@@ -XXX,XX +XXX,XX @@ static const unsigned int slave_boot_code[] = {
15
0x4c000020, /* jirl $r0,$r1,0 */
16
};
17
18
+static inline void *guidcpy(void *dst, const void *src)
19
+{
20
+ return memcpy(dst, src, sizeof(efi_guid_t));
21
+}
22
+
23
+static void init_efi_boot_memmap(struct efi_system_table *systab,
24
+ void *p, void *start)
25
+{
26
+ unsigned i;
27
+ struct efi_boot_memmap *boot_memmap = p;
28
+ efi_guid_t tbl_guid = LINUX_EFI_BOOT_MEMMAP_GUID;
29
+
30
+ /* efi_configuration_table 1 */
31
+ guidcpy(&systab->tables[0].guid, &tbl_guid);
32
+ systab->tables[0].table = (struct efi_configuration_table *)(p - start);
33
+ systab->nr_tables = 1;
34
+
35
+ boot_memmap->desc_size = sizeof(efi_memory_desc_t);
36
+ boot_memmap->desc_ver = 1;
37
+ boot_memmap->map_size = 0;
38
+
39
+ efi_memory_desc_t *map = p + sizeof(struct efi_boot_memmap);
40
+ for (i = 0; i < memmap_entries; i++) {
41
+ map = (void *)boot_memmap + sizeof(*map);
42
+ map[i].type = memmap_table[i].type;
43
+ map[i].phys_addr = memmap_table[i].address;
44
+ map[i].num_pages = memmap_table[i].length >> 16; /* 64KB align*/
45
+ p += sizeof(efi_memory_desc_t);
46
+ }
47
+}
48
+
49
static void init_systab(struct loongarch_boot_info *info, void *p, void *start)
50
{
51
+ void *bp_tables_start;
52
struct efi_system_table *systab = p;
53
54
info->a2 = (uint64_t)p - (uint64_t)start;
55
@@ -XXX,XX +XXX,XX @@ static void init_systab(struct loongarch_boot_info *info, void *p, void *start)
56
p += ROUND_UP(sizeof(struct efi_system_table), 64);
57
58
systab->tables = p;
59
+ bp_tables_start = p;
60
+
61
+ init_efi_boot_memmap(systab, p, start);
62
+ p += ROUND_UP(sizeof(struct efi_boot_memmap) +
63
+ sizeof(efi_memory_desc_t) * memmap_entries, 64);
64
+
65
+ systab->tables = (struct efi_configuration_table *)(bp_tables_start - start);
66
}
67
68
static void init_cmdline(struct loongarch_boot_info *info, void *p, void *start)
69
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/hw/loongarch/virt.c
72
+++ b/hw/loongarch/virt.c
73
@@ -XXX,XX +XXX,XX @@ static void virt_powerdown_req(Notifier *notifier, void *opaque)
74
acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS);
75
}
76
77
-struct memmap_entry {
78
- uint64_t address;
79
- uint64_t length;
80
- uint32_t type;
81
- uint32_t reserved;
82
-};
83
-
84
-static struct memmap_entry *memmap_table;
85
-static unsigned memmap_entries;
86
+struct memmap_entry *memmap_table;
87
+unsigned memmap_entries;
88
89
static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type)
90
{
91
diff --git a/include/hw/loongarch/boot.h b/include/hw/loongarch/boot.h
92
index XXXXXXX..XXXXXXX 100644
93
--- a/include/hw/loongarch/boot.h
94
+++ b/include/hw/loongarch/boot.h
95
@@ -XXX,XX +XXX,XX @@ typedef struct {
96
uint8_t b[16];
97
} efi_guid_t __attribute__((aligned(8)));
98
99
+#define EFI_GUID(a, b, c, d...) (efi_guid_t){ { \
100
+ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \
101
+ (b) & 0xff, ((b) >> 8) & 0xff, \
102
+ (c) & 0xff, ((c) >> 8) & 0xff, d } }
103
+
104
+#define LINUX_EFI_BOOT_MEMMAP_GUID \
105
+ EFI_GUID(0x800f683f, 0xd08b, 0x423a, 0xa2, 0x93, \
106
+ 0x96, 0x5c, 0x3c, 0x6f, 0xe2, 0xb4)
107
+
108
struct efi_config_table {
109
efi_guid_t guid;
110
uint64_t *ptr;
111
@@ -XXX,XX +XXX,XX @@ struct efi_system_table {
112
struct efi_configuration_table *tables;
113
};
114
115
+typedef struct {
116
+ uint32_t type;
117
+ uint32_t pad;
118
+ uint64_t phys_addr;
119
+ uint64_t virt_addr;
120
+ uint64_t num_pages;
121
+ uint64_t attribute;
122
+} efi_memory_desc_t;
123
+
124
+struct efi_boot_memmap {
125
+ uint64_t map_size;
126
+ uint64_t desc_size;
127
+ uint32_t desc_ver;
128
+ uint64_t map_key;
129
+ uint64_t buff_size;
130
+ efi_memory_desc_t map[32];
131
+};
132
+
133
struct loongarch_boot_info {
134
uint64_t ram_size;
135
const char *kernel_filename;
136
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
137
index XXXXXXX..XXXXXXX 100644
138
--- a/include/hw/loongarch/virt.h
139
+++ b/include/hw/loongarch/virt.h
140
@@ -XXX,XX +XXX,XX @@
141
142
#define COMMAND_LINE_SIZE 512
143
144
+extern struct memmap_entry *memmap_table;
145
+extern unsigned memmap_entries;
146
+
147
+struct memmap_entry {
148
+ uint64_t address;
149
+ uint64_t length;
150
+ uint32_t type;
151
+ uint32_t reserved;
152
+};
153
+
154
struct LoongArchMachineState {
155
/*< private >*/
156
MachineState parent_obj;
157
--
158
2.34.1
diff view generated by jsdifflib
New patch
[PULL v2 07/17] hw/loongarch: Init efi_initrd table
1
Signed-off-by: Song Gao <gaosong@loongson.cn>
2
Message-Id: <20240301093839.663947-8-gaosong@loongson.cn>
3
---
4
hw/loongarch/boot.c | 23 +++++++++++++++++++++--
5
include/hw/loongarch/boot.h | 9 +++++++++
6
2 files changed, 30 insertions(+), 2 deletions(-)
1
7
8
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/hw/loongarch/boot.c
11
+++ b/hw/loongarch/boot.c
12
@@ -XXX,XX +XXX,XX @@
13
#include "qemu/error-report.h"
14
#include "sysemu/reset.h"
15
16
+ram_addr_t initrd_offset;
17
+uint64_t initrd_size;
18
+
19
static const unsigned int slave_boot_code[] = {
20
/* Configure reset ebase. */
21
0x0400302c, /* csrwr $r12,0xc */
22
@@ -XXX,XX +XXX,XX @@ static void init_efi_boot_memmap(struct efi_system_table *systab,
23
}
24
}
25
26
+static void init_efi_initrd_table(struct efi_system_table *systab,
27
+ void *p, void *start)
28
+{
29
+ efi_guid_t tbl_guid = LINUX_EFI_INITRD_MEDIA_GUID;
30
+ struct efi_initrd *initrd_table = p;
31
+
32
+ /* efi_configuration_table 2 */
33
+ guidcpy(&systab->tables[1].guid, &tbl_guid);
34
+ systab->tables[1].table = (struct efi_configuration_table *)(p - start);
35
+ systab->nr_tables = 2;
36
+
37
+ initrd_table->base = initrd_offset;
38
+ initrd_table->size = initrd_size;
39
+}
40
+
41
static void init_systab(struct loongarch_boot_info *info, void *p, void *start)
42
{
43
void *bp_tables_start;
44
@@ -XXX,XX +XXX,XX @@ static void init_systab(struct loongarch_boot_info *info, void *p, void *start)
45
init_efi_boot_memmap(systab, p, start);
46
p += ROUND_UP(sizeof(struct efi_boot_memmap) +
47
sizeof(efi_memory_desc_t) * memmap_entries, 64);
48
+ init_efi_initrd_table(systab, p, start);
49
+ p += ROUND_UP(sizeof(struct efi_initrd), 64);
50
51
systab->tables = (struct efi_configuration_table *)(bp_tables_start - start);
52
}
53
@@ -XXX,XX +XXX,XX @@ static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
54
55
static int64_t load_kernel_info(struct loongarch_boot_info *info)
56
{
57
- uint64_t kernel_entry, kernel_low, kernel_high, initrd_size;
58
- ram_addr_t initrd_offset;
59
+ uint64_t kernel_entry, kernel_low, kernel_high;
60
ssize_t kernel_size;
61
62
kernel_size = load_elf(info->kernel_filename, NULL,
63
diff --git a/include/hw/loongarch/boot.h b/include/hw/loongarch/boot.h
64
index XXXXXXX..XXXXXXX 100644
65
--- a/include/hw/loongarch/boot.h
66
+++ b/include/hw/loongarch/boot.h
67
@@ -XXX,XX +XXX,XX @@ typedef struct {
68
EFI_GUID(0x800f683f, 0xd08b, 0x423a, 0xa2, 0x93, \
69
0x96, 0x5c, 0x3c, 0x6f, 0xe2, 0xb4)
70
71
+#define LINUX_EFI_INITRD_MEDIA_GUID \
72
+ EFI_GUID(0x5568e427, 0x68fc, 0x4f3d, 0xac, 0x74, \
73
+ 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68)
74
+
75
struct efi_config_table {
76
efi_guid_t guid;
77
uint64_t *ptr;
78
@@ -XXX,XX +XXX,XX @@ struct efi_boot_memmap {
79
efi_memory_desc_t map[32];
80
};
81
82
+struct efi_initrd {
83
+ uint64_t base;
84
+ uint64_t size;
85
+};
86
+
87
struct loongarch_boot_info {
88
uint64_t ram_size;
89
const char *kernel_filename;
90
--
91
2.34.1
diff view generated by jsdifflib
New patch
[PULL v2 08/17] hw/loongarch: Init efi_fdt table
1
Signed-off-by: Song Gao <gaosong@loongson.cn>
2
Message-Id: <20240301093839.663947-9-gaosong@loongson.cn>
3
---
4
hw/loongarch/boot.c | 11 +++++++++++
5
include/hw/loongarch/boot.h | 4 ++++
6
2 files changed, 15 insertions(+)
1
7
8
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/hw/loongarch/boot.c
11
+++ b/hw/loongarch/boot.c
12
@@ -XXX,XX +XXX,XX @@ static void init_efi_initrd_table(struct efi_system_table *systab,
13
initrd_table->size = initrd_size;
14
}
15
16
+static void init_efi_fdt_table(struct efi_system_table *systab)
17
+{
18
+ efi_guid_t tbl_guid = DEVICE_TREE_GUID;
19
+
20
+ /* efi_configuration_table 3 */
21
+ guidcpy(&systab->tables[2].guid, &tbl_guid);
22
+ systab->tables[2].table = (void *)0x100000; /* fdt_base 1MiB */
23
+ systab->nr_tables = 3;
24
+}
25
+
26
static void init_systab(struct loongarch_boot_info *info, void *p, void *start)
27
{
28
void *bp_tables_start;
29
@@ -XXX,XX +XXX,XX @@ static void init_systab(struct loongarch_boot_info *info, void *p, void *start)
30
sizeof(efi_memory_desc_t) * memmap_entries, 64);
31
init_efi_initrd_table(systab, p, start);
32
p += ROUND_UP(sizeof(struct efi_initrd), 64);
33
+ init_efi_fdt_table(systab);
34
35
systab->tables = (struct efi_configuration_table *)(bp_tables_start - start);
36
}
37
diff --git a/include/hw/loongarch/boot.h b/include/hw/loongarch/boot.h
38
index XXXXXXX..XXXXXXX 100644
39
--- a/include/hw/loongarch/boot.h
40
+++ b/include/hw/loongarch/boot.h
41
@@ -XXX,XX +XXX,XX @@ typedef struct {
42
EFI_GUID(0x5568e427, 0x68fc, 0x4f3d, 0xac, 0x74, \
43
0xca, 0x55, 0x52, 0x31, 0xcc, 0x68)
44
45
+#define DEVICE_TREE_GUID \
46
+ EFI_GUID(0xb1b621d5, 0xf19c, 0x41a5, 0x83, 0x0b, \
47
+ 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0)
48
+
49
struct efi_config_table {
50
efi_guid_t guid;
51
uint64_t *ptr;
52
--
53
2.34.1
diff view generated by jsdifflib
New patch
[PULL v2 09/17] hw/loongarch: Fix fdt memory node wrong 'reg'
1
The right fdt memory node like [1], not [2]
1
2
3
[1]
4
memory@0 {
5
device_type = "memory";
6
reg = <0x00 0x00 0x00 0x10000000>;
7
};
8
[2]
9
memory@0 {
10
device_type = "memory";
11
reg = <0x02 0x00 0x02 0x10000000>;
12
};
13
14
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
15
Signed-off-by: Song Gao <gaosong@loongson.cn>
16
Message-Id: <20240301093839.663947-10-gaosong@loongson.cn>
17
---
18
hw/loongarch/virt.c | 2 +-
19
1 file changed, 1 insertion(+), 1 deletion(-)
20
21
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/loongarch/virt.c
24
+++ b/hw/loongarch/virt.c
25
@@ -XXX,XX +XXX,XX @@ static void fdt_add_memory_node(MachineState *ms,
26
char *nodename = g_strdup_printf("/memory@%" PRIx64, base);
27
28
qemu_fdt_add_subnode(ms->fdt, nodename);
29
- qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
30
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, 0, size);
31
qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
32
33
if (ms->numa_state && ms->numa_state->num_nodes) {
34
--
35
2.34.1
diff view generated by jsdifflib
New patch
[PULL v2 10/17] hw/loongarch: fdt adds cpu interrupt controller node
1
fdt adds cpu interrupt controller node,
2
we use 'loongson,cpu-interrupt-controller'.
1
3
4
See:
5
https://github.com/torvalds/linux/blob/v6.7/drivers/irqchip/irq-loongarch-cpu.c
6
https://lore.kernel.org/r/20221114113824.1880-2-liupeibao@loongson.cn
7
8
Signed-off-by: Song Gao <gaosong@loongson.cn>
9
Message-Id: <20240301093839.663947-11-gaosong@loongson.cn>
10
---
11
hw/loongarch/virt.c | 21 +++++++++++++++++++++
12
1 file changed, 21 insertions(+)
13
14
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/loongarch/virt.c
17
+++ b/hw/loongarch/virt.c
18
@@ -XXX,XX +XXX,XX @@ static void virt_flash_map(LoongArchMachineState *lams,
19
virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem);
20
}
21
22
+static void fdt_add_cpuic_node(LoongArchMachineState *lams,
23
+ uint32_t *cpuintc_phandle)
24
+{
25
+ MachineState *ms = MACHINE(lams);
26
+ char *nodename;
27
+
28
+ *cpuintc_phandle = qemu_fdt_alloc_phandle(ms->fdt);
29
+ nodename = g_strdup_printf("/cpuic");
30
+ qemu_fdt_add_subnode(ms->fdt, nodename);
31
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *cpuintc_phandle);
32
+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
33
+ "loongson,cpu-interrupt-controller");
34
+ qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
35
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
36
+ g_free(nodename);
37
+}
38
+
39
static void fdt_add_flash_node(LoongArchMachineState *lams)
40
{
41
MachineState *ms = MACHINE(lams);
42
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
43
CPULoongArchState *env;
44
CPUState *cpu_state;
45
int cpu, pin, i, start, num;
46
+ uint32_t cpuintc_phandle;
47
48
/*
49
* The connection of interrupts:
50
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
51
memory_region_add_subregion(&lams->system_iocsr, MAIL_SEND_ADDR,
52
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
53
54
+ /* Add cpu interrupt-controller */
55
+ fdt_add_cpuic_node(lams, &cpuintc_phandle);
56
+
57
for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
58
cpu_state = qemu_get_cpu(cpu);
59
cpudev = DEVICE(cpu_state);
60
--
61
2.34.1
diff view generated by jsdifflib
[PULL 7/7] target/loongarch: Dump all generic CSR registers
[PULL v2 11/17] hw/loongarch: fdt adds Extend I/O Interrupt Controller
1
CSR registers is import system control registers, it had better
1
fdt adds Extend I/O Interrupt Controller,
2
dump all CSR registers when VM is running in system mode.
2
we use 'loongson,ls2k2000-eiointc'.
3
3
4
Here is dump output example of CSR registers:
4
See:
5
CSR000: CRMD b4 PRMD 4 EUEN 0 MISC 0
5
https://github.com/torvalds/linux/blob/v6.7/drivers/irqchip/irq-loongson-eiointc.c
6
CSR004: ECFG 71c1c ESTAT 0 ERA 9000000002c31300 BADV 12022c0e0
6
https://lore.kernel.org/r/764e02d924094580ac0f1d15535f4b98308705c6.1683279769.git.zhoubinbin@loongson.cn
7
CSR008: BADI 2b0000
8
CSR012: EENTRY 90000000046b0000
9
CSR016: TLBIDX ffffffff8e000228 TLBEHI 120228000 TLBELO0 400000016f19001f TLBELO1 400000016f1a401f
10
CSR024: ASID a0004 PGDL 90000001016f0000 PGDH 9000000004680000 PGD 0
11
CSR028: PWCL 5e56e PWCH 2e4 STLBPS e RVACFG 0
12
CSR032: CPUID 0 PRCFG1 72f8 PRCFG2 3ffff000 PRCFG3 8073f2
13
CSR048: SAVE0 0 SAVE1 af9c SAVE2 12010d6a8 SAVE3 8300000
14
CSR052: SAVE4 0 SAVE5 0 SAVE6 0 SAVE7 0
15
CSR064: TID 0 TCFG 8f0ca15 TVAL 4cefd8b CNTC fffffffffe688aaa
16
CSR068: TICLR 0
17
CSR096: LLBCTL 1
18
CSR136: TLBRENTRY 46ba000 TLBRBADV ffff8000130d81e2 TLBRERA 9000000003585cb8 TLBRSAVE ffff8000130d81e0
19
CSR140: TLBRELO0 1fe00043 TLBRELO1 40 TLBREHI ffff8000130d800e TLBRPRMD 0
20
CSR384: DMW0 8000000000000001 DMW1 9000000000000011 DMW2 0 DMW3 0
21
7
22
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
8
Signed-off-by: Song Gao <gaosong@loongson.cn>
9
Message-Id: <20240301093839.663947-12-gaosong@loongson.cn>
23
---
10
---
24
target/loongarch/cpu.c | 66 ++++++++++++++++++++++++++++++++----------
11
hw/loongarch/virt.c | 30 +++++++++++++++++++++++++++++-
25
target/loongarch/csr.c | 2 ++
12
include/hw/intc/loongarch_extioi.h | 1 +
26
target/loongarch/csr.h | 1 +
13
2 files changed, 30 insertions(+), 1 deletion(-)
27
3 files changed, 53 insertions(+), 16 deletions(-)
28
14
29
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
15
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
30
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
31
--- a/target/loongarch/cpu.c
17
--- a/hw/loongarch/virt.c
32
+++ b/target/loongarch/cpu.c
18
+++ b/hw/loongarch/virt.c
33
@@ -XXX,XX +XXX,XX @@ static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model)
19
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpuic_node(LoongArchMachineState *lams,
34
return oc;
20
g_free(nodename);
35
}
21
}
36
22
37
+static void loongarch_cpu_dump_csr(CPUState *cs, FILE *f)
23
+static void fdt_add_eiointc_node(LoongArchMachineState *lams,
24
+ uint32_t *cpuintc_phandle,
25
+ uint32_t *eiointc_phandle)
38
+{
26
+{
39
+#ifndef CONFIG_USER_ONLY
27
+ MachineState *ms = MACHINE(lams);
40
+ CPULoongArchState *env = cpu_env(cs);
28
+ char *nodename;
41
+ CSRInfo *csr_info;
29
+ hwaddr extioi_base = APIC_BASE;
42
+ int64_t *addr;
30
+ hwaddr extioi_size = EXTIOI_SIZE;
43
+ int i, j, len, col = 0;
44
+
31
+
45
+ qemu_fprintf(f, "\n");
32
+ *eiointc_phandle = qemu_fdt_alloc_phandle(ms->fdt);
46
+
33
+ nodename = g_strdup_printf("/eiointc@%" PRIx64, extioi_base);
47
+ /* Dump all generic CSR register */
34
+ qemu_fdt_add_subnode(ms->fdt, nodename);
48
+ for (i = 0; i < LOONGARCH_CSR_DBG; i++) {
35
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *eiointc_phandle);
49
+ csr_info = get_csr(i);
36
+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
50
+ if (!csr_info || (csr_info->flags & CSRFL_UNUSED)) {
37
+ "loongson,ls2k2000-eiointc");
51
+ if (i == (col + 3)) {
38
+ qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
52
+ qemu_fprintf(f, "\n");
39
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
53
+ }
40
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
54
+
41
+ *cpuintc_phandle);
55
+ continue;
42
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", 3);
56
+ }
43
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0,
57
+
44
+ extioi_base, 0x0, extioi_size);
58
+ if ((i > (col + 3)) || (i == col)) {
45
+ g_free(nodename);
59
+ col = i & ~3;
60
+ qemu_fprintf(f, " CSR%03d:", col);
61
+ }
62
+
63
+ addr = (void *)env + csr_info->offset;
64
+ qemu_fprintf(f, " %s ", csr_info->name);
65
+ len = strlen(csr_info->name);
66
+ for (; len < 6; len++) {
67
+ qemu_fprintf(f, " ");
68
+ }
69
+
70
+ qemu_fprintf(f, "%" PRIx64, *addr);
71
+ j = find_last_bit((void *)addr, BITS_PER_LONG) & (BITS_PER_LONG - 1);
72
+ len += j / 4 + 1;
73
+ for (; len < 22; len++) {
74
+ qemu_fprintf(f, " ");
75
+ }
76
+
77
+ if (i == (col + 3)) {
78
+ qemu_fprintf(f, "\n");
79
+ }
80
+ }
81
+ qemu_fprintf(f, "\n");
82
+#endif
83
+}
46
+}
84
+
47
+
85
static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
48
static void fdt_add_flash_node(LoongArchMachineState *lams)
86
{
49
{
87
CPULoongArchState *env = cpu_env(cs);
50
MachineState *ms = MACHINE(lams);
88
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
51
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
52
CPULoongArchState *env;
53
CPUState *cpu_state;
54
int cpu, pin, i, start, num;
55
- uint32_t cpuintc_phandle;
56
+ uint32_t cpuintc_phandle, eiointc_phandle;
57
58
/*
59
* The connection of interrupts:
60
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
89
}
61
}
90
}
62
}
91
63
92
- qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD);
64
+ /* Add Extend I/O Interrupt Controller node */
93
- qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD);
65
+ fdt_add_eiointc_node(lams, &cpuintc_phandle, &eiointc_phandle);
94
- qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN);
66
+
95
- qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT);
67
pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
96
- qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA);
68
num = VIRT_PCH_PIC_IRQ_NUM;
97
- qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV);
69
qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
98
- qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI);
70
diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
99
- qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY);
100
- qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 ","
101
- " PRCFG3=%016" PRIx64 "\n",
102
- env->CSR_PRCFG1, env->CSR_PRCFG2, env->CSR_PRCFG3);
103
- qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
104
- qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
105
- qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
106
- qemu_fprintf(f, "TCFG=%016" PRIx64 "\n", env->CSR_TCFG);
107
- qemu_fprintf(f, "TVAL=%016" PRIx64 "\n", env->CSR_TVAL);
108
+ /* csr */
109
+ loongarch_cpu_dump_csr(cs, f);
110
111
/* fpr */
112
if (flags & CPU_DUMP_FPU) {
113
diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
114
index XXXXXXX..XXXXXXX 100644
71
index XXXXXXX..XXXXXXX 100644
115
--- a/target/loongarch/csr.c
72
--- a/include/hw/intc/loongarch_extioi.h
116
+++ b/target/loongarch/csr.c
73
+++ b/include/hw/intc/loongarch_extioi.h
117
@@ -XXX,XX +XXX,XX @@
74
@@ -XXX,XX +XXX,XX @@
118
75
#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
119
#define CSR_OFF_FUNCS(NAME, FL, RD, WR) \
76
#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
120
[LOONGARCH_CSR_##NAME] = { \
77
#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
121
+ .name = (stringify(NAME)), \
78
+#define EXTIOI_SIZE 0x800
122
.offset = offsetof(CPULoongArchState, CSR_##NAME), \
79
123
.flags = FL, .readfn = RD, .writefn = WR \
80
typedef struct ExtIOICore {
124
}
81
uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
125
126
#define CSR_OFF_ARRAY(NAME, N) \
127
[LOONGARCH_CSR_##NAME(N)] = { \
128
+ .name = (stringify(NAME##N)), \
129
.offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
130
.flags = 0, .readfn = NULL, .writefn = NULL \
131
}
132
diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
133
index XXXXXXX..XXXXXXX 100644
134
--- a/target/loongarch/csr.h
135
+++ b/target/loongarch/csr.h
136
@@ -XXX,XX +XXX,XX @@ enum {
137
};
138
139
typedef struct {
140
+ const char *name;
141
int offset;
142
int flags;
143
GenCSRFunc readfn;
144
--
82
--
145
2.43.5
83
2.34.1
diff view generated by jsdifflib
New patch
[PULL v2 12/17] hw/loongarch: fdt adds pch_pic Controller
1
fdt adds pch pic controller, we use 'loongson,pch-pic-1.0'
1
2
3
See:
4
https://github.com/torvalds/linux/blob/v6.7/drivers/irqchip/irq-loongson-pch-pic.c
5
https://lore.kernel.org/r/20200528152757.1028711-4-jiaxun.yang@flygoat.com
6
7
Signed-off-by: Song Gao <gaosong@loongson.cn>
8
Message-Id: <20240301093839.663947-13-gaosong@loongson.cn>
9
---
10
hw/loongarch/virt.c | 30 +++++++++++++++++++++++++++++-
11
include/hw/pci-host/ls7a.h | 1 +
12
2 files changed, 30 insertions(+), 1 deletion(-)
13
14
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/loongarch/virt.c
17
+++ b/hw/loongarch/virt.c
18
@@ -XXX,XX +XXX,XX @@ static void fdt_add_eiointc_node(LoongArchMachineState *lams,
19
g_free(nodename);
20
}
21
22
+static void fdt_add_pch_pic_node(LoongArchMachineState *lams,
23
+ uint32_t *eiointc_phandle,
24
+ uint32_t *pch_pic_phandle)
25
+{
26
+ MachineState *ms = MACHINE(lams);
27
+ char *nodename;
28
+ hwaddr pch_pic_base = VIRT_PCH_REG_BASE;
29
+ hwaddr pch_pic_size = VIRT_PCH_REG_SIZE;
30
+
31
+ *pch_pic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
32
+ nodename = g_strdup_printf("/platic@%" PRIx64, pch_pic_base);
33
+ qemu_fdt_add_subnode(ms->fdt, nodename);
34
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_pic_phandle);
35
+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
36
+ "loongson,pch-pic-1.0");
37
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0,
38
+ pch_pic_base, 0, pch_pic_size);
39
+ qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
40
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 2);
41
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
42
+ *eiointc_phandle);
43
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,pic-base-vec", 0);
44
+ g_free(nodename);
45
+}
46
+
47
static void fdt_add_flash_node(LoongArchMachineState *lams)
48
{
49
MachineState *ms = MACHINE(lams);
50
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
51
CPULoongArchState *env;
52
CPUState *cpu_state;
53
int cpu, pin, i, start, num;
54
- uint32_t cpuintc_phandle, eiointc_phandle;
55
+ uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle;
56
57
/*
58
* The connection of interrupts:
59
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
60
qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
61
}
62
63
+ /* Add PCH PIC node */
64
+ fdt_add_pch_pic_node(lams, &eiointc_phandle, &pch_pic_phandle);
65
+
66
pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
67
start = num;
68
num = EXTIOI_IRQS - start;
69
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
70
index XXXXXXX..XXXXXXX 100644
71
--- a/include/hw/pci-host/ls7a.h
72
+++ b/include/hw/pci-host/ls7a.h
73
@@ -XXX,XX +XXX,XX @@
74
#define VIRT_PCH_REG_BASE 0x10000000UL
75
#define VIRT_IOAPIC_REG_BASE (VIRT_PCH_REG_BASE)
76
#define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL
77
+#define VIRT_PCH_REG_SIZE 0x400
78
79
/*
80
* GSI_BASE is hard-coded with 64 in linux kernel, else kernel fails to boot
81
--
82
2.34.1
diff view generated by jsdifflib
[PULL 3/7] target/loongarch: Add generic csr function type
[PULL v2 13/17] hw/loongarch: fdt adds pch_msi Controller
1
Parameter type TCGv and TCGv_ptr for function GenCSRRead and GenCSRWrite
1
fdt adds pch msi controller, we use 'loongson,pch-msi-1.0'.
2
is not used in non-TCG mode. Generic csr function type is added here
3
with parameter void type, so that it passes to compile with non-TCG mode.
4
2
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
3
See:
4
https://github.com/torvalds/linux/blob/v6.7/drivers/irqchip/irq-loongson-pch-msi.c
5
https://lore.kernel.org/r/20200528152757.1028711-6-jiaxun.yang@flygoat.com
6
7
Signed-off-by: Song Gao <gaosong@loongson.cn>
8
Message-Id: <20240301093839.663947-14-gaosong@loongson.cn>
6
---
9
---
7
.../tcg/insn_trans/trans_privileged.c.inc | 27 ++++++++++++-------
10
hw/loongarch/virt.c | 33 ++++++++++++++++++++++++++++++++-
8
1 file changed, 17 insertions(+), 10 deletions(-)
11
include/hw/pci-host/ls7a.h | 1 +
12
2 files changed, 33 insertions(+), 1 deletion(-)
9
13
10
diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
14
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
11
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
12
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
16
--- a/hw/loongarch/virt.c
13
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
17
+++ b/hw/loongarch/virt.c
14
@@ -XXX,XX +XXX,XX @@ GEN_FALSE_TRANS(idle)
18
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pch_pic_node(LoongArchMachineState *lams,
15
19
g_free(nodename);
16
typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
20
}
17
typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
21
18
+typedef void (*GenCSRFunc)(void);
22
+static void fdt_add_pch_msi_node(LoongArchMachineState *lams,
19
23
+ uint32_t *eiointc_phandle,
20
typedef struct {
24
+ uint32_t *pch_msi_phandle)
21
int offset;
25
+{
22
int flags;
26
+ MachineState *ms = MACHINE(lams);
23
- GenCSRRead readfn;
27
+ char *nodename;
24
- GenCSRWrite writefn;
28
+ hwaddr pch_msi_base = VIRT_PCH_MSI_ADDR_LOW;
25
+ GenCSRFunc readfn;
29
+ hwaddr pch_msi_size = VIRT_PCH_MSI_SIZE;
26
+ GenCSRFunc writefn;
30
+
27
} CSRInfo;
31
+ *pch_msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
28
32
+ nodename = g_strdup_printf("/msi@%" PRIx64, pch_msi_base);
29
enum {
33
+ qemu_fdt_add_subnode(ms->fdt, nodename);
30
@@ -XXX,XX +XXX,XX @@ static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn,
34
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_msi_phandle);
31
return false;
35
+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
36
+ "loongson,pch-msi-1.0");
37
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "reg",
38
+ 0, pch_msi_base,
39
+ 0, pch_msi_size);
40
+ qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
41
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
42
+ *eiointc_phandle);
43
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-base-vec",
44
+ VIRT_PCH_PIC_IRQ_NUM);
45
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-num-vecs",
46
+ EXTIOI_IRQS - VIRT_PCH_PIC_IRQ_NUM);
47
+ g_free(nodename);
48
+}
49
+
50
static void fdt_add_flash_node(LoongArchMachineState *lams)
51
{
52
MachineState *ms = MACHINE(lams);
53
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
54
CPULoongArchState *env;
55
CPUState *cpu_state;
56
int cpu, pin, i, start, num;
57
- uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle;
58
+ uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle;
59
60
/*
61
* The connection of interrupts:
62
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
63
qdev_get_gpio_in(extioi, i + start));
32
}
64
}
33
65
34
- csr->readfn = readfn;
66
+ /* Add PCH MSI node */
35
- csr->writefn = writefn;
67
+ fdt_add_pch_msi_node(lams, &eiointc_phandle, &pch_msi_phandle);
36
+ csr->readfn = (GenCSRFunc)readfn;
68
+
37
+ csr->writefn = (GenCSRFunc)writefn;
69
loongarch_devices_init(pch_pic, lams);
38
return true;
39
}
70
}
40
71
41
@@ -XXX,XX +XXX,XX @@ static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a)
72
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
42
{
73
index XXXXXXX..XXXXXXX 100644
43
TCGv dest;
74
--- a/include/hw/pci-host/ls7a.h
44
const CSRInfo *csr;
75
+++ b/include/hw/pci-host/ls7a.h
45
+ GenCSRRead readfn;
76
@@ -XXX,XX +XXX,XX @@
46
77
#define VIRT_IOAPIC_REG_BASE (VIRT_PCH_REG_BASE)
47
if (check_plv(ctx)) {
78
#define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL
48
return false;
79
#define VIRT_PCH_REG_SIZE 0x400
49
@@ -XXX,XX +XXX,XX @@ static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a)
80
+#define VIRT_PCH_MSI_SIZE 0x8
50
} else {
81
51
check_csr_flags(ctx, csr, false);
82
/*
52
dest = gpr_dst(ctx, a->rd, EXT_NONE);
83
* GSI_BASE is hard-coded with 64 in linux kernel, else kernel fails to boot
53
- if (csr->readfn) {
54
- csr->readfn(dest, tcg_env);
55
+ readfn = (GenCSRRead)csr->readfn;
56
+ if (readfn) {
57
+ readfn(dest, tcg_env);
58
} else {
59
tcg_gen_ld_tl(dest, tcg_env, csr->offset);
60
}
61
@@ -XXX,XX +XXX,XX @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
62
{
63
TCGv dest, src1;
64
const CSRInfo *csr;
65
+ GenCSRWrite writefn;
66
67
if (check_plv(ctx)) {
68
return false;
69
@@ -XXX,XX +XXX,XX @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
70
return false;
71
}
72
src1 = gpr_src(ctx, a->rd, EXT_NONE);
73
- if (csr->writefn) {
74
+ writefn = (GenCSRWrite)csr->writefn;
75
+ if (writefn) {
76
dest = gpr_dst(ctx, a->rd, EXT_NONE);
77
- csr->writefn(dest, tcg_env, src1);
78
+ writefn(dest, tcg_env, src1);
79
} else {
80
dest = tcg_temp_new();
81
tcg_gen_ld_tl(dest, tcg_env, csr->offset);
82
@@ -XXX,XX +XXX,XX @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
83
{
84
TCGv src1, mask, oldv, newv, temp;
85
const CSRInfo *csr;
86
+ GenCSRWrite writefn;
87
88
if (check_plv(ctx)) {
89
return false;
90
@@ -XXX,XX +XXX,XX @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
91
tcg_gen_andc_tl(temp, oldv, mask);
92
tcg_gen_or_tl(newv, newv, temp);
93
94
- if (csr->writefn) {
95
- csr->writefn(oldv, tcg_env, newv);
96
+ writefn = (GenCSRWrite)csr->writefn;
97
+ if (writefn) {
98
+ writefn(oldv, tcg_env, newv);
99
} else {
100
tcg_gen_st_tl(newv, tcg_env, csr->offset);
101
}
102
--
84
--
103
2.43.5
85
2.34.1
diff view generated by jsdifflib
[PULL 1/7] target/loongarch: Add dynamic function access with CSR register
[PULL v2 14/17] hw/loongarch: fdt adds pcie irq_map node
1
With CSR register, dynamic function access is used for CSR register
1
Signed-off-by: Song Gao <gaosong@loongson.cn>
2
access in TCG mode, so that csr info can be used by other modules.
2
Message-Id: <20240301093839.663947-15-gaosong@loongson.cn>
3
---
4
hw/loongarch/virt.c | 73 ++++++++++++++++++++++++++++++++++++++++++---
5
1 file changed, 69 insertions(+), 4 deletions(-)
3
6
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
7
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
5
---
6
.../tcg/insn_trans/trans_privileged.c.inc | 37 +++++++++++++++++--
7
target/loongarch/tcg/tcg_loongarch.h | 12 ++++++
8
target/loongarch/tcg/translate.c | 5 +++
9
3 files changed, 51 insertions(+), 3 deletions(-)
10
create mode 100644 target/loongarch/tcg/tcg_loongarch.h
11
12
diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
13
index XXXXXXX..XXXXXXX 100644
8
index XXXXXXX..XXXXXXX 100644
14
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
9
--- a/hw/loongarch/virt.c
15
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
10
+++ b/hw/loongarch/virt.c
16
@@ -XXX,XX +XXX,XX @@ enum {
11
@@ -XXX,XX +XXX,XX @@ static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams)
17
#define CSR_OFF(NAME) \
12
g_free(nodename);
18
CSR_OFF_FLAGS(NAME, 0)
19
20
-static const CSRInfo csr_info[] = {
21
+static CSRInfo csr_info[] = {
22
CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB),
23
CSR_OFF(PRMD),
24
CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
25
@@ -XXX,XX +XXX,XX @@ static bool check_plv(DisasContext *ctx)
26
return false;
27
}
13
}
28
14
29
-static const CSRInfo *get_csr(unsigned csr_num)
15
-static void fdt_add_pcie_node(const LoongArchMachineState *lams)
30
+static CSRInfo *get_csr(unsigned csr_num)
16
+static void fdt_add_pcie_irq_map_node(const LoongArchMachineState *lams,
31
{
17
+ char *nodename,
32
- const CSRInfo *csr;
18
+ uint32_t *pch_pic_phandle)
33
+ CSRInfo *csr;
34
35
if (csr_num >= ARRAY_SIZE(csr_info)) {
36
return NULL;
37
@@ -XXX,XX +XXX,XX @@ static const CSRInfo *get_csr(unsigned csr_num)
38
return csr;
39
}
40
41
+static bool set_csr_trans_func(unsigned int csr_num, GenCSRRead readfn,
42
+ GenCSRWrite writefn)
43
+{
19
+{
44
+ CSRInfo *csr;
20
+ int pin, dev;
21
+ uint32_t irq_map_stride = 0;
22
+ uint32_t full_irq_map[GPEX_NUM_IRQS *GPEX_NUM_IRQS * 10] = {};
23
+ uint32_t *irq_map = full_irq_map;
24
+ const MachineState *ms = MACHINE(lams);
45
+
25
+
46
+ csr = get_csr(csr_num);
26
+ /* This code creates a standard swizzle of interrupts such that
47
+ if (!csr) {
27
+ * each device's first interrupt is based on it's PCI_SLOT number.
48
+ return false;
28
+ * (See pci_swizzle_map_irq_fn())
29
+ *
30
+ * We only need one entry per interrupt in the table (not one per
31
+ * possible slot) seeing the interrupt-map-mask will allow the table
32
+ * to wrap to any number of devices.
33
+ */
34
+
35
+ for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
36
+ int devfn = dev * 0x8;
37
+
38
+ for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
39
+ int irq_nr = 16 + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
40
+ int i = 0;
41
+
42
+ /* Fill PCI address cells */
43
+ irq_map[i] = cpu_to_be32(devfn << 8);
44
+ i += 3;
45
+
46
+ /* Fill PCI Interrupt cells */
47
+ irq_map[i] = cpu_to_be32(pin + 1);
48
+ i += 1;
49
+
50
+ /* Fill interrupt controller phandle and cells */
51
+ irq_map[i++] = cpu_to_be32(*pch_pic_phandle);
52
+ irq_map[i++] = cpu_to_be32(irq_nr);
53
+
54
+ if (!irq_map_stride) {
55
+ irq_map_stride = i;
56
+ }
57
+ irq_map += irq_map_stride;
58
+ }
49
+ }
59
+ }
50
+
60
+
51
+ csr->readfn = readfn;
61
+
52
+ csr->writefn = writefn;
62
+ qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", full_irq_map,
53
+ return true;
63
+ GPEX_NUM_IRQS * GPEX_NUM_IRQS *
64
+ irq_map_stride * sizeof(uint32_t));
65
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
66
+ 0x1800, 0, 0, 0x7);
54
+}
67
+}
55
+
68
+
56
+#define SET_CSR_FUNC(NAME, read, write) \
69
+static void fdt_add_pcie_node(const LoongArchMachineState *lams,
57
+ set_csr_trans_func(LOONGARCH_CSR_##NAME, read, write)
70
+ uint32_t *pch_pic_phandle,
71
+ uint32_t *pch_msi_phandle)
72
{
73
char *nodename;
74
hwaddr base_mmio = VIRT_PCI_MEM_BASE;
75
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pcie_node(const LoongArchMachineState *lams)
76
2, base_pio, 2, size_pio,
77
1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
78
2, base_mmio, 2, size_mmio);
79
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
80
+ 0, *pch_msi_phandle, 0, 0x10000);
58
+
81
+
59
+void loongarch_csr_translate_init(void)
82
+ fdt_add_pcie_irq_map_node(lams, nodename, pch_pic_phandle);
60
+{
61
+ SET_CSR_FUNC(ESTAT, NULL, gen_helper_csrwr_estat);
62
+ SET_CSR_FUNC(ASID, NULL, gen_helper_csrwr_asid);
63
+ SET_CSR_FUNC(PGD, gen_helper_csrrd_pgd, NULL);
64
+ SET_CSR_FUNC(PWCL, NULL, gen_helper_csrwr_pwcl);
65
+ SET_CSR_FUNC(CPUID, gen_helper_csrrd_cpuid, NULL);
66
+ SET_CSR_FUNC(TCFG, NULL, gen_helper_csrwr_tcfg);
67
+ SET_CSR_FUNC(TVAL, gen_helper_csrrd_tval, NULL);
68
+ SET_CSR_FUNC(TICLR, NULL, gen_helper_csrwr_ticlr);
69
+}
70
+#undef SET_CSR_FUNC
71
+
83
+
72
static bool check_csr_flags(DisasContext *ctx, const CSRInfo *csr, bool write)
84
g_free(nodename);
85
}
86
87
@@ -XXX,XX +XXX,XX @@ static DeviceState *create_platform_bus(DeviceState *pch_pic)
88
return dev;
89
}
90
91
-static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams)
92
+static void loongarch_devices_init(DeviceState *pch_pic,
93
+ LoongArchMachineState *lams,
94
+ uint32_t *pch_pic_phandle,
95
+ uint32_t *pch_msi_phandle)
73
{
96
{
74
if ((csr->flags & CSRFL_READONLY) && write) {
97
MachineClass *mc = MACHINE_GET_CLASS(lams);
75
diff --git a/target/loongarch/tcg/tcg_loongarch.h b/target/loongarch/tcg/tcg_loongarch.h
98
DeviceState *gpex_dev;
76
new file mode 100644
99
@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
77
index XXXXXXX..XXXXXXX
100
gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i);
78
--- /dev/null
101
}
79
+++ b/target/loongarch/tcg/tcg_loongarch.h
102
80
@@ -XXX,XX +XXX,XX @@
103
+ /* Add pcie node */
81
+/* SPDX-License-Identifier: GPL-2.0-or-later */
104
+ fdt_add_pcie_node(lams, pch_pic_phandle, pch_msi_phandle);
82
+/*
83
+ * QEMU LoongArch TCG interface
84
+ *
85
+ * Copyright (c) 2025 Loongson Technology Corporation Limited
86
+ */
87
+#ifndef TARGET_LOONGARCH_TCG_LOONGARCH_H
88
+#define TARGET_LOONGARCH_TCG_LOONGARCH_H
89
+
105
+
90
+void loongarch_csr_translate_init(void);
106
serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0,
91
+
107
qdev_get_gpio_in(pch_pic,
92
+#endif /* TARGET_LOONGARCH_TCG_LOONGARCH_H */
108
VIRT_UART_IRQ - VIRT_GSI_BASE),
93
diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
109
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
94
index XXXXXXX..XXXXXXX 100644
110
/* Add PCH MSI node */
95
--- a/target/loongarch/tcg/translate.c
111
fdt_add_pch_msi_node(lams, &eiointc_phandle, &pch_msi_phandle);
96
+++ b/target/loongarch/tcg/translate.c
112
97
@@ -XXX,XX +XXX,XX @@
113
- loongarch_devices_init(pch_pic, lams);
98
#include "exec/log.h"
114
+ loongarch_devices_init(pch_pic, lams, &pch_pic_phandle, &pch_msi_phandle);
99
#include "qemu/qemu-print.h"
100
#include "fpu/softfloat.h"
101
+#include "tcg_loongarch.h"
102
#include "translate.h"
103
#include "internals.h"
104
#include "vec.h"
105
@@ -XXX,XX +XXX,XX @@ void loongarch_translate_init(void)
106
offsetof(CPULoongArchState, lladdr), "lladdr");
107
cpu_llval = tcg_global_mem_new(tcg_env,
108
offsetof(CPULoongArchState, llval), "llval");
109
+
110
+#ifndef CONFIG_USER_ONLY
111
+ loongarch_csr_translate_init();
112
+#endif
113
}
115
}
116
117
static void loongarch_firmware_init(LoongArchMachineState *lams)
118
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
119
lams->powerdown_notifier.notify = virt_powerdown_req;
120
qemu_register_powerdown_notifier(&lams->powerdown_notifier);
121
122
- fdt_add_pcie_node(lams);
123
/*
124
* Since lowmem region starts from 0 and Linux kernel legacy start address
125
* at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer
114
--
126
--
115
2.43.5
127
2.34.1
diff view generated by jsdifflib
New patch
[PULL v2 15/17] hw/loongarch: fdt remove unused irqchip node
1
Signed-off-by: Song Gao <gaosong@loongson.cn>
2
Message-Id: <20240301093839.663947-16-gaosong@loongson.cn>
3
---
4
hw/loongarch/virt.c | 31 +------------------------------
5
1 file changed, 1 insertion(+), 30 deletions(-)
1
6
7
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
8
index XXXXXXX..XXXXXXX 100644
9
--- a/hw/loongarch/virt.c
10
+++ b/hw/loongarch/virt.c
11
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pcie_node(const LoongArchMachineState *lams,
12
g_free(nodename);
13
}
14
15
-static void fdt_add_irqchip_node(LoongArchMachineState *lams)
16
-{
17
- MachineState *ms = MACHINE(lams);
18
- char *nodename;
19
- uint32_t irqchip_phandle;
20
-
21
- irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt);
22
- qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle);
23
-
24
- nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE);
25
- qemu_fdt_add_subnode(ms->fdt, nodename);
26
- qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
27
- qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
28
- qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
29
- qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
30
- qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
31
-
32
- qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
33
- "loongarch,ls7a");
34
-
35
- qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
36
- 2, VIRT_IOAPIC_REG_BASE,
37
- 2, PCH_PIC_ROUTE_ENTRY_OFFSET);
38
-
39
- qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle);
40
- g_free(nodename);
41
-}
42
-
43
static void fdt_add_memory_node(MachineState *ms,
44
uint64_t base, uint64_t size, int node_id)
45
{
46
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
47
48
/* Initialize the IO interrupt subsystem */
49
loongarch_irq_init(lams);
50
- fdt_add_irqchip_node(lams);
51
- platform_bus_add_all_fdt_nodes(machine->fdt, "/intc",
52
+ platform_bus_add_all_fdt_nodes(machine->fdt, "/platic",
53
VIRT_PLATFORM_BUS_BASEADDRESS,
54
VIRT_PLATFORM_BUS_SIZE,
55
VIRT_PLATFORM_BUS_IRQ);
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL v2 16/17] hw/loongarch: Add cells missing from uart node
1
uart node need interrupts and interrupt-parent cells.
1
2
3
Signed-off-by: Song Gao <gaosong@loongson.cn>
4
Message-Id: <20240301093839.663947-17-gaosong@loongson.cn>
5
---
6
hw/loongarch/virt.c | 9 +++++++--
7
1 file changed, 7 insertions(+), 2 deletions(-)
8
9
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/hw/loongarch/virt.c
12
+++ b/hw/loongarch/virt.c
13
@@ -XXX,XX +XXX,XX @@ static void fdt_add_rtc_node(LoongArchMachineState *lams)
14
g_free(nodename);
15
}
16
17
-static void fdt_add_uart_node(LoongArchMachineState *lams)
18
+static void fdt_add_uart_node(LoongArchMachineState *lams,
19
+ uint32_t *pch_pic_phandle)
20
{
21
char *nodename;
22
hwaddr base = VIRT_UART_BASE;
23
@@ -XXX,XX +XXX,XX @@ static void fdt_add_uart_node(LoongArchMachineState *lams)
24
qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size);
25
qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000);
26
qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
27
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
28
+ VIRT_UART_IRQ - VIRT_GSI_BASE, 0x4);
29
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
30
+ *pch_pic_phandle);
31
g_free(nodename);
32
}
33
34
@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic,
35
qdev_get_gpio_in(pch_pic,
36
VIRT_UART_IRQ - VIRT_GSI_BASE),
37
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
38
- fdt_add_uart_node(lams);
39
+ fdt_add_uart_node(lams, pch_pic_phandle);
40
41
/* Network init */
42
pci_init_nic_devices(pci_bus, mc->default_nic);
43
--
44
2.34.1
diff view generated by jsdifflib
[PULL 2/7] target/loongarch: Remove static CSR function setting
[PULL v2 17/17] hw/loongarch: Add cells missing from rtc node
1
Since CSR function setting is done dynamically in TCG mode, remove
1
rtc node need interrupts and interrupt-parent cells.
2
static CSR function setting here.
3
2
4
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
3
Signed-off-by: Song Gao <gaosong@loongson.cn>
4
Message-Id: <20240301093839.663947-18-gaosong@loongson.cn>
5
---
5
---
6
.../tcg/insn_trans/trans_privileged.c.inc | 16 ++++++++--------
6
hw/loongarch/virt.c | 12 +++++++++---
7
1 file changed, 8 insertions(+), 8 deletions(-)
7
1 file changed, 9 insertions(+), 3 deletions(-)
8
8
9
diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
9
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
10
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
11
--- a/hw/loongarch/virt.c
12
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
12
+++ b/hw/loongarch/virt.c
13
@@ -XXX,XX +XXX,XX @@ static CSRInfo csr_info[] = {
13
@@ -XXX,XX +XXX,XX @@ static void fdt_add_flash_node(LoongArchMachineState *lams)
14
CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
14
g_free(nodename);
15
CSR_OFF_FLAGS(MISC, CSRFL_READONLY),
15
}
16
CSR_OFF(ECFG),
16
17
- CSR_OFF_FUNCS(ESTAT, CSRFL_EXITTB, NULL, gen_helper_csrwr_estat),
17
-static void fdt_add_rtc_node(LoongArchMachineState *lams)
18
+ CSR_OFF_FLAGS(ESTAT, CSRFL_EXITTB),
18
+static void fdt_add_rtc_node(LoongArchMachineState *lams,
19
CSR_OFF(ERA),
19
+ uint32_t *pch_pic_phandle)
20
CSR_OFF(BADV),
20
{
21
CSR_OFF_FLAGS(BADI, CSRFL_READONLY),
21
char *nodename;
22
@@ -XXX,XX +XXX,XX @@ static CSRInfo csr_info[] = {
22
hwaddr base = VIRT_RTC_REG_BASE;
23
CSR_OFF(TLBEHI),
23
@@ -XXX,XX +XXX,XX @@ static void fdt_add_rtc_node(LoongArchMachineState *lams)
24
CSR_OFF(TLBELO0),
24
25
CSR_OFF(TLBELO1),
25
nodename = g_strdup_printf("/rtc@%" PRIx64, base);
26
- CSR_OFF_FUNCS(ASID, CSRFL_EXITTB, NULL, gen_helper_csrwr_asid),
26
qemu_fdt_add_subnode(ms->fdt, nodename);
27
+ CSR_OFF_FLAGS(ASID, CSRFL_EXITTB),
27
- qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc");
28
CSR_OFF(PGDL),
28
+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
29
CSR_OFF(PGDH),
29
+ "loongson,ls7a-rtc");
30
- CSR_OFF_FUNCS(PGD, CSRFL_READONLY, gen_helper_csrrd_pgd, NULL),
30
qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
31
- CSR_OFF_FUNCS(PWCL, 0, NULL, gen_helper_csrwr_pwcl),
31
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
32
+ CSR_OFF_FLAGS(PGD, CSRFL_READONLY),
32
+ VIRT_RTC_IRQ - VIRT_GSI_BASE , 0x4);
33
+ CSR_OFF(PWCL),
33
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
34
CSR_OFF(PWCH),
34
+ *pch_pic_phandle);
35
CSR_OFF(STLBPS),
35
g_free(nodename);
36
CSR_OFF(RVACFG),
36
}
37
- CSR_OFF_FUNCS(CPUID, CSRFL_READONLY, gen_helper_csrrd_cpuid, NULL),
37
38
+ CSR_OFF_FLAGS(CPUID, CSRFL_READONLY),
38
@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic,
39
CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY),
39
sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
40
CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY),
40
qdev_get_gpio_in(pch_pic,
41
CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY),
41
VIRT_RTC_IRQ - VIRT_GSI_BASE));
42
@@ -XXX,XX +XXX,XX @@ static CSRInfo csr_info[] = {
42
- fdt_add_rtc_node(lams);
43
CSR_OFF_ARRAY(SAVE, 14),
43
+ fdt_add_rtc_node(lams, pch_pic_phandle);
44
CSR_OFF_ARRAY(SAVE, 15),
44
45
CSR_OFF(TID),
45
/* acpi ged */
46
- CSR_OFF_FUNCS(TCFG, CSRFL_IO, NULL, gen_helper_csrwr_tcfg),
46
lams->acpi_ged = create_acpi_ged(pch_pic, lams);
47
- CSR_OFF_FUNCS(TVAL, CSRFL_READONLY | CSRFL_IO, gen_helper_csrrd_tval, NULL),
48
+ CSR_OFF_FLAGS(TCFG, CSRFL_IO),
49
+ CSR_OFF_FLAGS(TVAL, CSRFL_READONLY | CSRFL_IO),
50
CSR_OFF(CNTC),
51
- CSR_OFF_FUNCS(TICLR, CSRFL_IO, NULL, gen_helper_csrwr_ticlr),
52
+ CSR_OFF_FLAGS(TICLR, CSRFL_IO),
53
CSR_OFF(LLBCTL),
54
CSR_OFF(IMPCTL1),
55
CSR_OFF(IMPCTL2),
56
--
47
--
57
2.43.5
48
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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